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| this is information on a product in full production. december 2015 docid026415 rev 4 1/184 stm32f303xd stm32f303xe arm ? cortex ? -m4 32b mcu+fpu, up to 512kb flash, 80kb sram, fsmc, 4 adcs, 2 dac ch., 7 comp, 4 op-amp, 2.0-3.6 v datasheet - production data features ? core: arm ? cortex ? -m4 32-bit cpu with 72 mhz fpu, single-cycle multiplication and hw division, 90 dm ips (from ccm), dsp instruction and mpu (memory protection unit) ? operating conditions: ?v dd , v dda voltage range: 2.0 v to 3.6 v ? memories ? up to 512 kbytes of flash memory ? 64 kbytes of sram, with hw parity check implemented on the first 32 kbytes. ? routine booster: 16 kbytes of sram on instruction and data bus, with hw parity check (ccm) ? flexible memory controller (fsmc) for static memories, with four chip select ? crc calculation unit ? reset and supply management ? power-on/power-down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop and standby ?v bat supply for rtc and backup registers ? clock management ?4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x 16 pll option ? intern al 40 khz oscillator ? up to 115 fast i/os ? all mappable on external interrupt vectors ? several 5 v-tolerant ? interconnect matrix ? 12-channel dma controller ? four adcs 0.20 s (up to 40 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 v conversion range, separate analog supply from 2.0 to 3.6 v ? two 12-bit dac channels with analog supply from 2.4 to 3.6 v ? seven ultra-fast rail-to-rail analog comparators with analog supply from 2.0 to 3.6 v ? four operational amplifiers that can be used in pga mode, all terminals accessible with analog supply from 2.4 to 3.6 v ? up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensor s ? up to 14 timers ? one 32-bit timer and two 16-bit timers with up to four ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? three 16-bit 6-channel advanced-control timers, with up to six pwm channels, deadtime generation and emergency stop ? one 16-bit timer with two ic/ocs, one ocn/pwm, deadtime generation and emergency stop ? two 16-bit timers with ic/oc/ocn/pwm, deadtime generation and emergency stop ? two watchdog timers (independent, window) ? one systick timer: 24-bit downcounter ? two 16-bit basic timers to drive the dac ? calendar rtc with alarm, periodic wakeup from stop/standby ? communication interfaces ? can interface (2.0b active) ? three i 2 c fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, wakeup from stop ? up to five usart/uarts (iso 7816 interface, lin, irda, modem control) ? up to four spis, 4 to 16 programmable bit frames, two with multiplexed half/full duplex i2s interface ? usb 2.0 full speed interface with lpm support ? infrared transmitte r ? swd, cortex ? -m4 with fpu etm, jtag ? 96-bit unique id table 1. device summary reference part number stm32f303xd STM32F303RD, stm32f303vd, stm32f303zd. stm32f303xe stm32f303re, stm32f303ve, stm32f303ze. lqfp64 lqfp100 lqfp144 ufbga100 (10 10 mm) (14 14 mm) (20 x 20 mm) ) % * $ (7 x 7 mm) wlcsp100 ( 4.775 x 5.041 mm ) www.st.com
contents stm32f303xd stm32f303xe 2/184 docid026415 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 arm ? cortex ? -m4 core with fpu with embedded flash and sram . . . 15 3.2 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 22 3.14 fast analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.4 opamp reference voltage (vrefopamp) . . . . . . . . . . . . . . . . . . . . . . 23 3.15 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 ultra-fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 docid026415 rev 4 3/184 stm32f303xd stm32f303xe contents 4 3.18.1 advanced timers (tim1, tim8, tim20) . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) . . 26 3.18.3 basic timers (tim6, tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 27 3.20 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.21 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 29 3.22 universal asynchronous receiver transmitter (uart) . . . . . . . . . . . . . . . 30 3.23 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) . 31 3.24 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.25 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.26 infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.27 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.28 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.28.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.28.2 embedded trace macrocell ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 74 contents stm32f303xd stm32f303xe 4/184 docid026415 rev 4 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 74 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.11 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.12 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.13 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.3.14 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.15 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.16 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.17 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.18 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.19 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.20 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.21 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.22 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.23 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.24 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.1 lqfp144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.2 ufbga100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.3 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.4 wlcsp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.5 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.6.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.6.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 179 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 docid026415 rev 4 5/184 stm32f303xd stm32f303xe list of tables 7 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f303xd/e family device features and periph eral counts . . . . . . . . . . . . . . . . . . . . . 12 table 3. external analog supply values for analog peripheral s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. stm32f303xd/e peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. stm32f303xd/e i2c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. usart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. stm32f303xd/e spi/i2s implementati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. capacitive sensing gpios available on stm32f 303xd/e devices . . . . . . . . . . . . . . . . . . 33 table 11. number of capacitive sensing channels available on stm32f303xd/e devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. stm32f303xd/e pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. stm32f303xd/e alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 15. memory map, peripheral register boundary addresse s . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 16. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 17. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 18. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 19. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 20. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 21. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 22. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 23. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 table 24. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 25. typical and maximum current consumption from v dd supply at v dd = 3.6v . . . . . . . . . . . 78 table 26. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 79 table 27. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 80 table 28. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 80 table 29. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 81 table 30. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 31. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 83 table 32. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 33. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 34. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 35. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 36. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 37. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 38. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 39. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 40. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 41. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 42. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 43. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 44. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 100 table 45. asynchronous non-multiplexed sram/psram /nor read-nwait timings . . . . . . . . . . . 100 table 46. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 101 list of tables stm32f303xd stm32f303xe 6/184 docid026415 rev 4 table 47. asynchronous non-multiplexed sram/psram /nor write-nwait timings. . . . . . . . . . . 102 table 48. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 102 table 49. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 50. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 51. asynchronous multiplexed psram/nor write-nwai t timings . . . . . . . . . . . . . . . . . . . . 106 table 52. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 53. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 54. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 112 table 55. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 56. switching characteristics for pc card/cf read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 57. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . 118 table 58. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 59. switching characteristics for na nd flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 60. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 61. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 62. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 table 63. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 64. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 65. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 66. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 67. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 68. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 69. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 70. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 71. wwdg min-max timeout value @72 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 72. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 73. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 74. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 75. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 76. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 77. usb: full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 0 table 78. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 79. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 80. adc accuracy - limited test conditions, 100-/144-pi n packages . . . . . . . . . . . . . . . . . . . 146 table 81. adc accuracy, 100-pin/144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 82. adc accuracy - limited test conditions, 64-pin pack ages . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 83. adc accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 table 84. adc accuracy at 1msps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 85. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 86. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 87. operational amplifier characteristic s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 88. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 89. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 90. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 91. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 92. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 93. ufbga100 recommended pcb design rules (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . 167 table 94. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 docid026415 rev 4 7/184 stm32f303xd stm32f303xe list of tables 7 table 95. wlcsp100 ? 100l, 4.775 x 5.041 mm 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 96. wlcsp100 recommended pcb design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 174 table 97. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 98. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 99. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 100. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 list of figures stm32f303xd stm32f303xe 8/184 docid026415 rev 4 list of figures figure 1. stm32f303xd/e block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figure 2. stm32f303xd/e clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 3. infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 4. stm32f303xd/e lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 5. stm32f303xd/e lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 6. stm32f303xd/e lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 7. stm32f303xd/e wlcsp100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 8. stm32f303xd/e ufbga100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 9. stm32f303xd/e memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 12. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 13. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 14. typical v bat current consumption (lse and rtc on/lsedrv [1:0] 00?) . . . . . . . . . . . . . 81 figure 15. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 16. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 17. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 18. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 19. hsi oscillator accuracy char acterization results for soldered parts . . . . . . . . . . . . . . . . . . 96 figure 20. asynchronous non-multiple xed sram/psram/nor read timings . . . . . . . . . . . . . . . . . . 99 figure 21. asynchronous non-multiple xed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 101 figure 22. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 23. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 24. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 25. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 26. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 27. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 28. pc card/compactflash controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 29. pc card/compactflash controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 30. pc card/compactflash cont roller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 31. pc card/compactflash cont roller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 32. pc card/compactflash cont roller waveforms for i/o space read access . . . . . . . . . . . . 119 figure 33. pc card/compactflash cont roller waveforms for i/o space write access . . . . . . . . . . . . 119 figure 34. nand controller read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 35. nand controller write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 36. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 37. tc and tta i/o input characteri stics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 38. five volt tolerant (ft and ftf) i/o input char acteristics - cmos port. . . . . . . . . . . . . . . . 127 figure 39. five volt tolerant (ft and ftf) i/o input char acteristics - ttl port . . . . . . . . . . . . . . . . . . 128 figure 40. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 41. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 42. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 43. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 44. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 docid026415 rev 4 9/184 stm32f303xd stm32f303xe list of figures 9 figure 45. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 46. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 47. usb timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 48. adc typical current consumption on vdda pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 49. adc typical current consumption on vref+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 50. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 51. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 52. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 53. opamp voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 54. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 162 figure 55. lqfp144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 56. lqfp144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 57. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 figure 58. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 59. ufbga100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 60. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 169 figure 61. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 62. lqfp100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 63. wlcsp100 ? 100l, 4.775 x 5.041 mm 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 64. wlcsp100 ? 100l, 4.775 x 5.041 mm 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 65. wlcsp100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 66. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 176 figure 67. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 177 figure 68. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 69. lqfp100 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 introduction stm32f303xd stm32f303xe 10/184 docid026415 rev 4 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32f303xd/e microcontrollers. this stm32f303xd/e datasheet should be read in conjunction with the reference manual of stm32f303xb/c/d/e, stm32f358xc and stm32f 328x4/6/8 devices (rm0316) available on stmicroelectronics website at www.st.com . for information on the cortex ? -m4 core with fpu, please refer to the following documents: ? cortex ? -m4 with fpu technical reference manual , available from arm website at www.arm.com ? stm32f3 and stm32f4 series cortex ? -m4 programming manual (pm0214) available on stmicroelectronics website at www.st.com . docid026415 rev 4 11/184 stm32f303xd stm32f303xe description 67 2 description the stm32f303xd/e family is ba sed on the high-performance arm ? cortex ? -m4 32-bit risc core with fpu operating at a frequency of 72 mhz, and embedding a floating point unit (fpu), a memory protection unit (mpu ) and an embedded trace macrocell (etm). the family incorporates high-speed embedded memories (512 kbyte flash memory, 80 kbyte sram), a flexible memory controller (fsmc) for static memories (sram, psram, nor and nand), and an extensive range of enhanced i/os and peripherals connected to an ahb and two apb buses. the devices offer four fast 12-bit adcs (5 msps), seven comparators, four operational amplifiers, two dac channels, a low-power rtc, up to five general-purpose 16-bit timers, one general-purpose 32-bit timer, and three timers dedicated to motor control. they also feature standard and advanced communication interfaces: up to three i 2 cs, up to four spis (two spis are with mult iplexed full-duplex i 2 ss), three usarts, up to two uarts, can and usb. to achieve audio class accuracy, the i 2 s peripherals can be clocked via an external pll. the stm32f303xd/e family operates in the -40 to +85c and -40 to +105c temperature ranges from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f303xd/e family offers devices in different packages ranging from 64 pins to 144 pins. the set of included peripherals changes with the device chosen. description stm32f303xd stm32f303xe 12/184 docid026415 rev 4 table 2. stm32f303xd/e family device features and peripheral counts peripheral stm32f303rx stm32f303vx stm32f303zx flash (kbytes) 384 512 384 512 384 512 sram (kbytes) on data bus 64 ccm (core coupled memory) ram (kbytes) 16 fmc ( flexible memory controller) no yes timers advanced control 2 (16-bit) 3 (16-bit) general purpose 5 (16-bit) 1 (32-bit) pwm channels (all) (1) 31 40 40 basic 2 (16-bit) pwm channels (except complementary) 22 28 28 communication interfaces spi (i2s) (2) 4(2) i 2 c3 usart 3 uart 2 can 1 usb 1 gpios normal i/os (tc, tta) 26 37 in wlcsp100,44 in lqfp100 and ufbga100 45 5-volt tolerant i/os (ft, ftf) 25 42 in lqfp100 40 in wlcsp100 and ufbga100 70 dma channels 12 capacitive sensing channels 18 24 12-bit adcs 4 22 channels 4 39 channels in lqfp100-pin and ufbga100 33 channels in wlcsp100 4 40 channels 12-bit dac channels analog comparator operational amplifiers cpu frequency 72 mhz operating voltage 2.0 to 3.6 v docid026415 rev 4 13/184 stm32f303xd stm32f303xe description 67 operating temperature ambient operating temperature: - 40 to 85 c / - 40 to 105 c junction temperature: - 40 to 125 c packages lqfp64 lqfp100 ,wlcsp100 ufbga100 lqfp144 1. this total number considers also the pwms generated on the complementary output channels. 2. the spi interfaces can work in an exclusive way in either the spi mode or the i 2 s audio mode. table 2. stm32f303xd/e family device features and peripheral counts (continued) peripheral stm32f303rx stm32f303vx stm32f303zx description stm32f303xd stm32f303xe 14/184 docid026415 rev 4 figure 1. stm32f303xd/e block diagram 1. af: alternate function on i/o pins. 0 6 y 9 7 r x f k 6 h q v l q j & r q w u r o o h u 7 , 0 ( 5 & k d q q h o v & r p s & k d q q h o % 5 . d v $ ) 7 , 0 ( 5 7 , 0 ( 5 3 : 0 7 , 0 ( 5 3 : 0 & k d q q h o v & r p s f k d q q h o v ( 7 5 % 5 . d v $ ) 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 8 6 $ 5 7 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) : l q : $ 7 & + ' 2 * % x v 0 d w u l [ 0 3 8 ) 3 8 & r u w h [ 0 & 3 8 ) p d [ 0 + ] 1 9 , & * 3 ' 0 $ f k d q q h o v . % & & 0 5 $ 0 ) o d v k l q w h u i d f h 2 % / . % ) / $ 6 + e l w v - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 0 6 6 : ' , 2 - 7 ' 2 $ v $ ) 3 r z h u 9 r o w d j h u h j 9 w r 9 9 ' ' 6 x s s o \ 6 x s h u y l v l r q 3 2 5 3 ' 5 3 9 ' 3 2 5 5 h v h w , q w 9 ' ' , 2 w r 9 9 6 6 1 5 ( 6 ( 7 9 ' ' $ 9 6 6 $ , q g : ' * . 6 w d q g e \ l q w h u i d f h 3 / / # 9 ' ' , 2 # 9 ' ' $ ; 7 $ / 2 6 & 0 + ] 5 h v h w f o r f n f r q w u r o $ + % 3 & / . $ 3 % 3 & / . $ 3 % 3 & / . $ + % $ 3 % $ + % $ 3 % & 5 & $ 3 % ) p d [ 0 + ] $ 3 % i p d [ 0 + ] * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 ' 2 6 & b , 1 2 6 & b 2 8 7 6 3 , , 6 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 5 & / 6 7 , 0 ( 5 7 , 0 ( 5 6 3 , , 6 e l w ' $ & , ) # 9 ' ' $ 7 , 0 ( 5 e l w 3 : 0 3 % > @ 0 2 6 , 6 ' 0 , 6 2 h [ w b 6 ' 6 & . & . 1 6 6 : 6 0 & / . d v $ ) & k d q q h o v ( 7 5 d v $ ) 8 6 % b ' 3 8 6 % b ' 0 ' $ & b & + d v $ ) + & / . ) & / . 8 6 $ 5 7 & / . . % 6 5 $ 0 ( 7 0 7 u d f h 7 u l j 6 : - 7 $ * 7 3 , 8 , e x v 7 5 $ ' ( & / . 7 5 $ & ( ' > @ d v $ ) ' e x v 6 \ v w h p * 3 ' 0 $ f k d q q h o v e l w $ ' & e l w $ ' & , ) 7 h p s v h q v r u 9 5 ( ) 9 5 ( ) 7 , 0 ( 5 ( ; 7 , 7 : . 8 3 ; ; $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o v & r p s f k d q q h o v ( 7 5 % 5 . d v $ ) 3 ' > @ 7 , 0 ( 5 8 6 % 6 5 $ 0 % e l w $ ' & , ) e l w $ ' & , & & / . $ ' & 6 $ 5 & / . # 9 ' ' , 2 # 9 ' ' $ # 9 6 : ; 7 $ / n + ] 2 6 & b , 1 2 6 & b 2 8 7 9 % $ 7 9 w r 9 5 7 & $ : 8 % d f n x s 5 h j % \ w h % d f n x s l q w h u i d f h $ 1 7 , 7 $ 0 3 7 , 0 ( 5 8 $ 5 7 8 $ 5 7 , & , & e [ & $ 1 % 6 5 $ 0 8 6 % ) 6 ' $ & b & + d v $ ) 2 s $ p s 2 s $ p s 2 s $ p s 2 s $ p s # 9 ' ' $ , 1 [ [ 2 8 7 [ [ , 1 [ [ 2 8 7 [ [ , 1 [ [ 2 8 7 [ [ , 1 [ [ 2 8 7 [ [ , 1 7 ( 5 ) $ & ( 6 < 6 & ) * & 7 / * 3 & r p s d u d w r u * 3 & r p s d u d w r u & $ 1 7 ; & $ 1 5 ; & k d q q h o v ( 7 5 d v $ ) & k d q q h o v ( 7 5 d v $ ) 0 2 6 , 6 ' 0 , 6 2 h [ w b 6 ' 6 & . & . 1 6 6 : 6 0 & / . d v $ ) 5 ; 7 ; & 7 6 5 7 6 d v $ ) 5 ; 7 ; & 7 6 5 7 6 d v $ ) 5 ; 7 ; d v $ ) 5 ; 7 ; d v $ ) # 9 ' ' $ ; [ , q v 2 8 7 v d v $ ) ; ; * u r x s v r i f k d q q h o v d v $ ) $ + % $ + % * 3 & r p s d u d w r u 5 & + 6 0 + ] 7 , 0 ( 5 3 : 0 & k d q q h o v & r p s f k d q q h o v ( 7 5 % 5 . d v $ ) 6 & / 6 ' $ 6 0 % $ d v $ ) , & 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) ) 0 & 6 5 $ 0 3 6 5 $ 0 3 & & d u g & r p s d f w ) o d v k 1 2 5 1 $ 1 ' ) o d v k & / . 1 ( > @ $ > @ ' ^ @ 1 2 ( 1 1 : ( 1 1 % / > @ 6 ' & / . ( > @ 6 ' 1 ( > @ 6 ' 1 : ( 1 / 1 5 $ 6 1 & $ 6 1 $ ' 9 1 : $ , 7 1 , 2 5 ' 1 5 ( * & ' , 1 7 1 * 3 , 2 3 2 5 7 + 3 + > @ * 3 , 2 3 2 5 7 * 3 * > @ * 3 , 2 3 2 5 7 ) 3 ) > @ * 3 , 2 3 2 5 7 ( 3 ( > @ * 3 , 2 3 2 5 7 & 3 & > @ * 3 , 2 3 2 5 7 $ 3 $ > @ docid026415 rev 4 15/184 stm32f303xd stm32f303xe functional overview 67 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu with embedded flash and sram the arm ? cortex ? -m4 processor with fpu is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 32-bit risc processor with fpu features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the stm32f303xd/ e family is compatib le with all arm tools and software. figure 1 shows the general block diagram of the stm32f303xd/e family devices. 3.2 memory protection unit (mpu) the memory protection unit (mpu) is used to se parate the processing of tasks from the data protection. the mpu can manage up to 8 protection areas that can all be further divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the memory protection unit is especially help ful for applications w here some critical or certified code has to be protected against th e misbehavior of other tasks. it is usually managed by an rtos (real-time operating system). if a program accesses a memory location that is prohibited by the mpu, the rt os can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 3.3 embedded flash memory all stm32f303xd/e devices feature 384/512 kbyte of embedded flash memory available for storing programs and data. the flash memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). functional overview stm32f303xd stm32f303xe 16/184 docid026415 rev 4 3.4 embedded sram stm32f303xd/e devices feature 80 kbytes of embedded sram with hardware parity check. the memory can be acce ssed in read/write at cpu clock speed with 0 wait states, allowing the cpu to achieve 90 dhrystone mips at 72 mhz (when running code from the ccm (core coupled memory) ram). ? 16 kbytes of ccm sram mapped on both in struction and data bus, used to execute critical routines or to access data (parity check on all of ccm sram). ? 64 kbytes of sram mapped on the data bus (p arity check on first 32 kbytes of sram). 3.5 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in the system memory . it is used to reprogram the flash memory by using usart1 (pa9/pa10) , usart2 (pa2/pa3) or usb (pa11/pa12) through dfu (device firmware upgrade). 3.6 cyclic redund ancy check (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. docid026415 rev 4 17/184 stm32f303xd stm32f303xe functional overview 67 3.7 power management 3.7.1 power supply schemes ? v ss , v dd = 2.0 to 3.6 v : external power supply for i/os an d the internal regulator. it is provided externally through v dd pins. ? v ssa , v dda = 2.0 to 3.6 v: external analog power supply for adc, dac, comparators, operational amplifier, reset blocks, rcs and pll. the mi nimum voltage to be applied to v dda differs from one analog peripheral to another. table 3 provides the summary of the v dda ranges for analog peripherals. the v dda voltage level must always be greater than or equal to the v dd voltage level and must be provided first. ? v bat = 1.65 to 3.6 v: power supply for rt c, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.7.2 power supply supervisor the device has an integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.7.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr), and power-down. ? the mr mode is used in the nominal regulation mode (run) ? the lpr mode is used in stop mode. ? the power-down mode is used in standby mo de: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the voltage regulator is always enabled after reset. it is disabled in standby mode. table 3. external analog supply values for analog peripherals analog peripheral minimum v dda supply maximum v dda supply adc/comp 2.0 v 3.6 v dac/opamp 2.4 v 3.6 v functional overview stm32f303xd stm32f303xe 18/184 docid026415 rev 4 3.7.4 low-power modes the stm32f303xd/e supports three low-powe r modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the usb wakeup, the rtc alarm, compx, i2cx or u(s)artx. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin or an rtc alarm occurs. note: the rtc, the iwdg and the corresponding clock sources are not stopped by entering stop or standby mode. 3.8 interconnect matrix several peripherals have direct connecti ons between them. this allows autonomous communication between peripherals, savi ng cpu resources thus power supply consumption. in addition, these hardware co nnections allow fast and predictable latency. table 4. stm32f303xd/e peripheral interconnect matrix interconnect source interconnect destination interconnect action timx timx timers synchronization or chaining adcx dac1 conversion triggers dma memory to memory transfer trigger compx comparator output blanking compx timx timer input: ocref_clr input, input capture adcx timx timer triggered by analog watchdog docid026415 rev 4 19/184 stm32f303xd stm32f303xe functional overview 67 note: for more details about the interconnect action s, please refer to the corresponding sections in the stm32f303xd/ereference manual (rm0316). 3.9 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domain s. the maximum fr equency of the ah b and the high speed apb domains is 72 mhz, while the maximum allowe d frequency of the low speed apb domain is 36 mhz. gpio rtcclk hse/32 mc0 tim16 clock source used as input channel for hsi and lsi calibration css cpu (hard fault) compx gpio tim1, tim8, tim20 tim15, 16, 17 timer break gpio timx external trigger, timer break adcx dac1 conversion external trigger dac1 compx comparator inverting input table 4. stm32f303xd/e peripheral interconnect matrix (continued) interconnect source interconnect destination interconnect action functional overview stm32f303xd stm32f303xe 20/184 docid026415 rev 4 figure 2. stm32f303xd/e clock tree 0 6 9 , i $ 3 % s u h v f d o h u [ h o v h [ $ + % / 6 ( 6 : 6 < 6 & / . ) / , 7 ) & / . w r ) o d v k s u r j u d p p l q j l q w h u i d f h w r , & [ [ , 6 6 5 & 6 < 6 & / . ( [ w f o r f n w r , 6 [ [ 8 6 % s u h v f d o h u 8 6 % & / . w r 8 6 % l q w h u i d f h + & / . w r $ + % e x v f r u h p h p r u \ d q g ' 0 $ w r & r u w h [ v \ v w h p w l p h u ) + & / . & r u w h [ i u h h u x q q l q j f o r f n 3 / & / . + 6 , / 6 ( w r 7 , 0 w r 8 6 $ 5 7 [ [ w r 7 , 0 w r $ 3 % s h u l s k h u d o v 3 & / . w r 8 6 $ 5 7 7 , 0 w r $ ' & [ \ [ \ / 6 , 5 & n + ] 0 + ] + 6 ( 2 6 & 5 7 & & / . w r 5 7 & $ 3 % s u h v f d o h u 0 + ] + 6 , 5 & + 6 ( + 6 , 3 / / & / . 3 / / [ [ ? [ 3 / / 6 5 & 3 / / 0 8 / 3 5 ( ' , 9 w r ) 0 & + 6 , 6 < 6 & / . w r $ 3 % s h u l s k h u d o v 3 & / . , i $ 3 % s u h v f d o h u [ h o v h [ 3 & / . 6 < 6 & / . + 6 , / 6 ( $ 3 % s u h v f d o h u $ + % s u h v f d o h u $ ' & s u h v f d o h u $ ' & s u h v f d o h u [ 6 < 6 & / . 0 & 2 / 6 , + 6 ( + 6 , 3 / / & / . , : ' * & / . w r , : ' * / 6 , 5 7 & 6 ( / > @ 0 & 2 s u h v f d o h u 0 & 2 / 6 ( 2 6 & n + ] & 6 6 + 6 , , 6 b & . , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b , 1 2 6 & b 2 8 7 docid026415 rev 4 21/184 stm32f303xd stm32f303xe functional overview 67 3.10 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allows i/o toggling up to 36 mhz. 3.11 direct memo ry access (dma) the flexible general-purpose dma is able to manage memory-to-memory, peripheral-to- memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrup ts when the controller reaches the end of the buffer. each of the 12 dma channels is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers, dac and adc. 3.12 flexible static me mory controller (fsmc) the flexible static memory controller (fsmc) includes two memory controllers: ? the nor/psram memory controller, ? the nand/pc card memory controller. this memory controller is also named flexible memory controller (fmc). the main features of the fmc controller are the following: ? interface with static-memory mapped devices including: ? static random access memory (sram), ? nor flash memory/onenand flash memory, ? psram (four memory banks), ? nand flash memory with e cc hardware to check up to 8 kbyte of data, ? 16-bit pc card compatible devices. ? 8-,16-bit data bus width, ? independent chip select control for each memory bank, ? independent configuration for each memory bank, ? write fifo, ? lcd parallel interface. the fmc can be configured to interface seam lessly with most grap hic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost functional overview stm32f303xd stm32f303xe 22/184 docid026415 rev 4 effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.13 interrupts and events 3.13.1 nested vectored inte rrupt controller (nvic) the stm32f303xd/e devices embed a nested vect ored interrupt controller (nvic) able to handle up to 73 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14 fast analog-to-digital converter (adc) four fast analog-to-digital co nverters 5 msps, with selectab le resolution between 12 and 6 bit, are embedded in the stm32f303xd/e family devices. the adcs have up to 40 external channels. some of the external channels are shared between adc1&2 and between adc3&4. the adcs can perform conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adcs have also internal channels: temp erature sensor connected to adc1 channel 16, vbat/2 connected to adc1 channel 17, voltage reference vrefint connected to the 4 adcs channel 18, vrefopamp1 connect ed to adc1 channel 15, vrefopamp2 connected to adc2 channel 17, vrefopamp3 connected to adc3 channel 17 and vrefopamp4 connected to adc4 channel 17. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold ? single-shunt phase current reading techniques. the adc can be served by the dma controller. three analog watchdogs are available per adc. the analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interr upt is generated when the converted voltage is outside the programmed thresholds. docid026415 rev 4 23/184 stm32f303xd stm32f303xe functional overview 67 the events generated by the general-purpose timers and the advan ced-control timers (tim1, tim8 and tim20) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the applicatio n to synchronize a/d conversion and timers. 3.14.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.14.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally con nected to the adcx_in18, x=1...4 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memo ry area. it is accessible in read-only mode. 3.14.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc1_in17. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.14.4 opamp reference voltage (vrefopamp) every opamp reference voltage can be measured using a corresponding adc internal channel: vrefopamp1 connected to adc1 channel 15, vrefopamp2 connected to adc2 channel 17, vrefopamp3 connected to adc3 channel 17 and vrefopamp4 connected to adc4 channel 17. functional overview stm32f303xd stm32f303xe 24/184 docid026415 rev 4 3.15 digital-to-analog converter (dac) two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inve rting configuration. this digital interface supp orts the following features: ? two dac output channels ? 8-bit or 10-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability (for each channel) ? external triggers for conversion ? input voltage reference vref+ 3.16 operational amplifier (opamp) the stm32f303xd/e embed four operational amplifiers with external or internal follower routing and pga capability (or ev en amplifier and filter capab ility with external components). when an operational amplifier is selected, an external adc channel is used to enable output measurement. the operational amplifier features: ? 8.2 mhz bandwidth ? 0.5 ma output capability ? rail-to-rail input/output ? in pga mode, the gain can be programmed to be 2, 4, 8 or 16. 3.17 ultra-fast comparators (comp) the stm32f303xd/e devices embed seven ul tra-fast rail-to-rail comparators with programmable reference voltage (internal or external) and selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output pin ? internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 23: embedded internal reference voltage for the value and precision of the internal reference voltage. all comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator. docid026415 rev 4 25/184 stm32f303xd stm32f303xe functional overview 67 3.18 timers and watchdogs the stm32f303xd/e include three advanced co ntrol timers, up to six general-purpose timers, two basic timers, two watchdog timers and one systick timer. the table below compares the features of the advanced co ntrol, general purpose and basic timers. note: tim1/8/20/2/3/4/15/16/17 can have pll as cl ock source, and therefore can be clocked at 144 mhz. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced tim1, tim8, tim20 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim15 16-bit up any integer between 1 and 65536 yes 2 1 general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no functional overview stm32f303xd stm32f303xe 26/184 docid026415 rev 4 3.18.1 advanced timers (tim1, tim8, tim20) the advanced-control timers (tim1, tim8, ti m20) can each be seen as a three-phase pwm multiplexed on six channels. they have complementary pwm outputs with programmable inserted dead-times. they can also be seen as complete general-purpose timers. the four independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or cent er-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose tim timers (described in section 3.18.2 using the same architecture, so t he advanced-control timers can work together with the tim timers via the timer link feature for synchronization or event chaining. 3.18.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) there are up to six synchronizable general-purpose timers embedded in the stm32f303xd/e (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. ? tim2, 3, and tim4 these are full-featured general-purpose timers: ? tim2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler ? tim3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers. these timers all feature 4 independent chan nels for input capture/output compare, pwm or one-pulse mode output. they can work together, or with the other general- purpose timers via the timer link featur e for synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generat ion and support quadrature encoders. ? tim15, 16 and 17 these three timers general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.18.3 basic timers (tim6, tim7) these timers are mainly used for dac trigge r generation. they can also be used as a generic 16-bit time base. docid026415 rev 4 27/184 stm32f303xd stm32f303xe functional overview 67 3.18.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.18.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.18.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source 3.19 real-time clock (rtc ) and backup registers the rtc and the 16 backup registers are supplied through a switch that takes power from either the v dd supply when present or the v bat pin. the backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when v dd power is not present. they are not reset by a system or power rese t, or when the device wakes up from standby mode. functional overview stm32f303xd stm32f303xe 28/184 docid026415 rev 4 the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? automatic correction for 28, 29 (leap year), 30 and 31 days of the month. ? two programmable alarms with wake up fr om stop and standb y mode capability. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy. ? three anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? 17-bit auto-reload counter for periodic interrupt with wakeup from stop/standby capability. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32. 3.20 inter-integrated ci rcuit interface (i2c) up to three i2c bus interfaces can operate in multimaster and slave modes. they can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes. all i2c bus interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. docid026415 rev 4 29/184 stm32f303xd stm32f303xe functional overview 67 in addition, they provide hard ware support for sm bus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) gener ation/verification, timeouts verifications and alert protocol management. they also have a clock domain independent from the cpu clock, allowing the i2cx (x=1,2,3) to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to table 7 for the features availabl e in i2c1, i2c2 and i2c3. 3.21 universal synchronous/asynch ronous receiver transmitter (usart) the stm32f303xd/e devices have three embedded universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3). the usart interfaces are able to communicate at speeds of up to 9 mbit/s. they provide hardware management of the ct s and rts signals, they support irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode and have li n master/slave capability. the usart interfaces can be served by the dma controller. table 7. stm32f303xd/e i2c implementation i2c features (1) i2c1 i2c2 i2c3 7-bit addressing mode x x x 10-bit addressing mode x x x standard mode (up to 100 kbit/s) x x x fast mode (up to 400 kbit/s) x x x fast mode plus with 20ma output dr ive i/os (up to 1 mbit/s) x x x independent clock x x x smbus x x x wakeup from stop x x x 1. x = supported. functional overview stm32f303xd stm32f303xe 30/184 docid026415 rev 4 3.22 universal asynchronous receiver transmitter (uart) the stm32f303xd/e devices have 2 embedded universal asynchronous receiver transmitters (uart4, and uart5). the uart interfaces suppor t irda sir endec, multiprocessor communication mode and single-wire half-duplex communication mode. the uart4 interface can be served by the dma controller. refer to table 8 for the features available in all u(s)art interfaces. table 8. usart features usart modes/features (1) usart1 usart2 usart3 uart4 uart5 hardware flow control for modem x x x - - continuous communication using dma x x x x - multiprocessor communication x x x x x synchronous mode x x x - - smartcard mode x x x - - single-wire half-duplex communication x x x x x irda sir endec block x x x x x lin mode xxxxx dual clock domain and wakeup from stop mode x x x x x receiver timeout interrupt xxxxx modbus communication x x x x x auto baud rate detection x x x - - driver enable x x x - - 1. x = supported. docid026415 rev 4 31/184 stm32f303xd stm32f303xe functional overview 67 3.23 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) up to four spis are able to communicate up to 18 mbit/s in slave and master modes in full- duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. two standard i2s interfaces (multiplexed with spi2 and spi3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. they can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by 8-bit programmable linear prescaler. when operating in master mode it can output a clo ck for an external audio component at 256 times the sampling frequency. refer to table 9 for the features available in spi1, spi2, spi3 and spi4. 3.24 controller area network (can) the can is compliant with specif ications 2.0a and b (active) wit h a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 3.25 universal serial bus (usb) the stm32f303xd/e embeds a full-speed usb device peripheral compliant with the usb specification version 2.0. the usb interface implements a full-speed (12 mbit/s) function interface with added support for usb 2.0 link power management. it has software- configurable endpoint setting with packet memory up-to 1 kbyte (256 bytes are used for can peripheral if enabled) and suspend/resume support. the dedicated 48 mhz clock is generated from the internal main pll (the clock source must use a hse crystal oscillator). table 9. stm32f303xd/e spi/i2s implementation spi features (1) spi1 spi2 spi3 spi4 hardware crc calculation xxxx rx/tx fifo xxxx nss pulse mode xxxx i2s mode - x x - ti mode xxxx 1. x = supported. functional overview stm32f303xd stm32f303xe 32/184 docid026415 rev 4 3.26 infrared transmitter the stm32f303xd/e devices provide an infrared transmitter solution. th e solution is based on internal connections between tim16 and tim17 as shown in the figure below. tim17 is used to provide the carrier frequenc y and tim16 provides the main signal to be sent. the infrared output signal is available on pb9 or pa13. to generate the infrared remote control sign als, tim16 channel 1 and tim17 channel 1 must be properly configured to generate correct waveforms. all standard ir pulse modulation modes can be obtained by programming t he two timers output compare channels. figure 3. infrared transmitter 3.27 touch sensing controller (tsc) the stm32f303xd/e devices provide a simple solution for adding capacitive sensing functionality to any application. these device s offer up to 24 capacitive sensing channels distributed over 8 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, etc.). the capacitive variation introduced by the finger (or any conduct ive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor unt il the voltage across this capa citor has reached a specific threshold. to limit the cpu bandwidth usage th is acquisition is dire ctly managed by the hardware touch sensing controller and only r equires few external components to operate. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library which is free to use and allows touch se nsing functionality to be implemented reliably in the end application. 7 , 0 ( 5 i r u h q y h o r s 7 , 0 ( 5 i r u f d u u l h u 2 & 2 & 3 % 3 $ 0 6 y 9 docid026415 rev 4 33/184 stm32f303xd stm32f303xe functional overview 67 table 10. capacitive sensing gp ios available on stm32f303xd/e devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 5 tsc_g5_io1 pb3 tsc_g1_io2 pa1 tsc_g5_io2 pb4 tsc_g1_io3 pa2 tsc_g5_io3 pb6 tsc_g1_io4 pa3 tsc_g5_io4 pb7 2 tsc_g2_io1 pa4 6 tsc_g6_io1 pb11 tsc_g2_io2 pa5 tsc_g6_io2 pb12 tsc_g2_io3 pa6 tsc_g6_io3 pb13 tsc_g2_io4 pa7 tsc_g6_io4 pb14 3 tsc_g3_io1 pc5 7 tsc_g7_io1 pe2 tsc_g3_io2 pb0 tsc_g7_io2 pe3 tsc_g3_io3 pb1 tsc_g7_io3 pe4 tsc_g3_io4 pb2 tsc_g7_io4 pe5 4 tsc_g4_io1 pa9 8 tsc_g8_io1 pd12 tsc_g4_io2 pa10 tsc_g8_io2 pd13 tsc_g4_io3 pa13 tsc_g8_io3 pd14 tsc_g4_io4 pa14 tsc_g8_io4 pd15 table 11. number of capacitive sensing channels available on stm32f303xd/e devices analog i/o group number of capacitive sensing channels stm32f303ve/ze stm32f303re g1 3 3 g2 3 3 g3 3 3 g4 3 3 g5 3 3 g6 3 3 g7 3 0 g8 3 0 number of capacitive sensing channels 24 18 functional overview stm32f303xd stm32f303xe 34/184 docid026415 rev 4 3.28 development support 3.28.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared re spectively with swdio and swclk and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. 3.28.2 embedded trace macrocell ? the arm embedded trace ma crocell provides a greater visib ility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f303xd/e through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using a high-speed channel. real-time instruction and data flow ac tivity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools. docid026415 rev 4 35/184 stm32f303xd stm32f303xe pinouts and pin description 67 4 pinouts and pin description figure 4. stm32f303xd/e lqfp64 pinout 0 6 9 9 % $ 7 3 & 2 6 & b , 1 3 ) 2 6 & b , 1 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 9 6 6 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 3 % / 4 ) 3 3 & 9 ' ' 9 6 6 9 ' ' 9 6 6 3 ) 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 pinouts and pin description stm32f303xd stm32f303xe 36/184 docid026415 rev 4 figure 5. stm32f303xd/e lqfp100 pinout 0 6 9 9 ' ' 9 6 6 3 ) 3 $ 3 $ 3 $ 3 $ 3 & 2 6 & b , 1 3 $ 3 & 2 6 & b 2 8 7 3 $ 3 ) 3 & 3 ) 3 & 3 ) 2 6 & b , 1 3 & 3 ) 2 & 6 b 2 8 7 3 & 1 5 6 7 3 ' 3 & 3 ' 3 & 3 ' 3 & 3 ' 3 & 3 ' 3 ) 3 ' 9 6 6 $ 9 5 ( ) 3 ' 9 5 ( ) 3 ' 9 ' ' $ 3 % 3 $ 3 % 3 $ 3 % 3 $ 3 % 3 $ 3 ( 3 ( 3 ( 3 ( 3 ( 9 ' ' 9 6 6 3 ( 3 ( 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 & 3 & 3 & 3 $ 3 $ / 4 ) 3 3 & 9 % $ 7 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 3 % 9 6 6 9 ' ' 9 ' ' 9 6 6 3 $ docid026415 rev 4 37/184 stm32f303xd stm32f303xe pinouts and pin description 67 figure 6. stm32f303xd/e lqfp144 pinout 0 6 9 3 ( 3 ( 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 * 3 * 3 * 3 * 3 * 3 * 3 * 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 & 3 & 3 & 3 $ 3 $ 3 ( 3 ( 3 ( 3 ( 3 $ 3 ( 3 $ 9 % $ 7 3 $ 3 $ 3 $ 3 & 3 & 3 ) 3 & 3 ) 3 & 3 ) 3 ) 3 * 3 * 3 ) 3 * 3 ) 3 * 3 ) 3 * 3 ) 3 * 3 ) 3 * 3 ' 3 ' 1 5 6 7 3 & 3 & 3 ' 3 & 3 ' 3 & 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 ) 3 ) 3 ) 3 ) 3 ) 3 * 3 * 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 3 % / 4 ) 3 9 ' ' 9 6 6 9 ' ' 9 6 6 9 ' ' 9 6 6 3 & b $ 1 7 , b 7 $ 0 3 3 & b 2 6 & b , 1 3 + 3 + 9 6 6 9 ' ' 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 9 6 6 $ 9 5 ( ) 9 5 ( ) 9 ' ' $ 3 $ b : . 8 3 3 $ 3 $ 9 6 6 9 ' ' 9 6 6 9 ' ' 9 6 6 9 ' ' 9 6 6 9 ' ' 9 6 6 9 ' ' 9 6 6 9 ' ' 3 $ 3 + 9 6 6 9 ' ' 3 & b 2 6 & b 2 8 7 pinouts and pin description stm32f303xd stm32f303xe 38/184 docid026415 rev 4 figure 7. stm32f303xd/e wlcsp100 ballout 0 6 y 9 $ % & ' ( ) * + - . 3 $ 3 $ 3 $ 3 $ 3 $ % 2 2 7 3 ( 9 6 6 3 ( 3 ( 3 $ 3 ( 3 ( 9 ' ' 3 % 3 % 3 % 3 % 3 % 3 $ 3 & 3 & 3 $ 3 % 3 % 3 % 3 % 3 % 3 ( 3 ( 3 & 3 ' 3 % 3 % 3 % 3 ' 3 ' 3 ' 3 ' 3 & 3 & 3 $ 3 & 3 ' 3 ' 3 % 3 % 3 ' 3 ' 3 & 3 & 3 ' 3 ' 3 % 9 6 6 9 6 6 3 $ 3 $ 9 ' ' 3 $ 3 & 3 ' 3 ' 9 6 6 9 6 6 9 6 6 9 6 6 3 ) 3 $ 3 $ 3 & 9 6 6 $ 9 5 ( ) 9 ' ' 3 ( 3 ( 9 ' ' 3 ( 9 % $ 7 3 ) 3 ) 2 6 & , 1 3 & 3 & 9 ' ' $ 9 6 6 9 ' ' 9 ' ' 3 & 2 6 & , 1 3 ) 3 ) 3 & 3 & 2 6 & 2 8 7 1 5 6 7 3 & 3 $ 3 $ 9 6 6 3 ) 2 6 & 2 8 7 9 ' ' 3 ( docid026415 rev 4 39/184 stm32f303xd stm32f303xe pinouts and pin description 67 figure 8. stm32f303xd/e ufbga100 ballout 0 6 9 $ % ( ' & ) * + - . / 0 3 ( 3 & 3 & 3 ( 3 & 3 ) 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 ( 3 ( 3 ( 3 ( 9 % $ 7 3 ) 3 ) 1 5 6 7 3 & 3 & 3 $ 3 $ 3 % 3 ( 3 % 9 6 6 9 6 6 9 ' ' 3 & 3 $ 3 $ 3 $ % 2 2 7 3 % 9 ' ' 3 $ 3 $ 3 $ 3 ' 3 % 3 % 3 & 3 & 3 % 3 ' 3 ' 3 % 3 % 3 % 3 ' 3 ( 3 ( 3 % 3 ' 3 ' 3 ' 3 ( 3 ( 3 $ 3 ' 3 ' 3 ' 3 ( 3 ( 3 $ 3 & 3 & 3 & 3 $ 3 ' 3 ' 3 % 3 % 3 ( 3 $ 3 & 3 ) 3 $ 3 & 3 ' 3 ' 3 % 3 % 3 ( 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 & 3 & 3 ' 3 ' 3 % 3 % 3 ( 9 6 6 9 ' ' 3 & 3 ) 2 6 & , 1 3 ) 2 6 & 2 8 7 pinouts and pin description stm32f303xd stm32f303xe 40/184 docid026415 rev 4 table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, i2c fm+ option tta 3.3 v tolerant i/o tc standard 3.3v i/o b dedicated to boot0 pin rst bi-directional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected thro ugh gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers docid026415 rev 4 41/184 stm32f303xd stm32f303xe pinouts and pin description 67 table 13. stm32f303xd/e pin definitions pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 - 1 b2 d6 1 pe2 i/o ft (1) traceck, eventout, tim3_ch1, tsc_g7_io1, spi4_sck, tim20_ch1, fmc_a23 - - 2 a1 d7 2 pe3 i/o ft (1) traced0, eventout, tim3_ch2, tsc_g7_io2, spi4_nss, tim20_ch2, fmc_a19 - - 3 b1 c8 3 pe4 i/o ft (1) traced1, eventout, tim3_ch3, tsc_g7_io3, spi4_nss, tim20_ch1n, fmc_a20 - - 4 c2 b9 4 pe5 i/o ft (1) traced2, eventout, tim3_ch4, tsc_g7_io4, spi4_miso, tim20_ch2n, fmc_a21 - - 5 d2 e7 5 pe6 i/o ft (1) traced3, eventout, spi4_mosi, tim20_ch3n, fmc_a22 wkup3, rtc_tamp3 1 6 e2 d8 6 vbat s - - - - 2 7 c1 c9 7 pc13 (2) i/o tc - eventout, tim1_ch1n wkup2,rtc_tamp1, rtc_ts, rtc_out 3 8 d1 c10 8 pc14 - osc32_in (2) i/o tc - eventout osc32_in 49 e1d99 pc15 - osc32_out (2) i/o tc - eventout osc32_out - - - - 10 ph0 i/o ft (1) eventout, tim20_ch1, fmc_a0 - - - - - 11 ph1 i/o ft (1) eventout, tim20_ch2, fmc_a1 - - 19 j1 e8 12 pf2 i/o tta (1) eventout, tim20_ch3, fmc_a2 adc12_in10 - - - - 13 pf3 i/o ft (1) eventout, tim20_ch4, fmc_a3 - pinouts and pin description stm32f303xd stm32f303xe 42/184 docid026415 rev 4 - - - - 14 pf4 i/o tta (1) eventout, comp1_out, tim20_ch1n, fmc_a4 adc1_in5 - - - - 15 pf5 i/o ft (1) eventout, tim20_ch2n, fmc_a5 - - - - - 16 vss s (1) -- -- - - 17vdd s (1) -- - 73 c11 c1 18 pf6 i/o ftf (1) eventout, tim4_ch4, i2c2_scl, usart3_rts, fmc_niord - - - - - 19 pf7 i/o ft (1) eventout, tim20_bkin, fmc_nreg - - - - - 20 pf8 i/o ft (1) eventout, tim20_bkin2, fmc_niowr - - 10 f2 d10 21 pf9 i/o ft (1) eventout, tim20_bkin, tim15_ch1, spi2_sck, fmc_cd - - 11 g2 e10 22 pf10 i/o ft (1) eventout, tim20_bkin2, tim15_ch2, spi2_sck, fmc_intr - 5 12 f1 f10 23 pf0-osc_in i ftf - eventout, i2c2_sda, spi2_nss/i2s2_ws, tim1_ch3n osc_in 613g1f924 pf1- osc_out oftf- eventout, i2c2_scl, spi2_sck/i2s2_ck osc_out 7 14 h2 e9 25 nrst i-o rst - device reset input/internal reset output (active low) 8 15 h1 g10 26 pc0 i/o tta - eventout, tim1_ch1 adc12_in6, comp7_inm 9 16 j2 g9 27 pc1 i/o tta - eventout, tim1_ch2 adc12_in7, comp7_inp 10 17 j3 g8 28 pc2 i/o tta - eventout, tim1_ch3, comp7_out adc12_in8 table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 docid026415 rev 4 43/184 stm32f303xd stm32f303xe pinouts and pin description 67 11 18 k2 h10 29 pc3 i/o tta - eventout, tim1_ch4, tim1_bkin2 adc12_in9 12 20 k1 h8 30 vssa s - (1) -- - - - - 31 vref- s - (1) -- -21m1j832vref+ (3) s- -- - 13 22 l1 j10 33 vdda s - - - - 14 23 l2 h9 34 pa0 i/o tta - tim2_ch1/tim2_etr, tsc_g1_io1, usart2_cts, comp1_out, tim8_bkin, tim8_etr, eventout adc1_in1, comp1_inm, rtc_tamp2, wkup1 15 24 m2 j9 35 pa1 i/o tta - rtc_refin, tim2_ch2, tsc_g1_io2, usart2_rts, tim15_ch1n, eventout adc1_in2, comp1_inp, opamp1_vinp, opamp3_vinp 16 25 k3 f7 36 pa2 i/o tta (4) tim2_ch3, tsc_g1_io3, usart2_tx, comp2_out, tim15_ch1, eventout adc1_in3, comp2_inm, opamp1_vout 17 26 l3 g7 37 pa3 i/o tta - tim2_ch4, tsc_g1_io4, usart2_rx, tim15_ch2, eventout adc1_in4, opamp1_vinm opamp,1_vinp 18 27 d3 k9, k10 38 vss s - - - - 19 28 h3 k8 39 vdd s - (1) -- 20 29 m3 j7 40 pa4 i/o tta (4) tim3_ch2, tsc_g2_io1, spi1_nss, spi3_nss/i2s3_ws, usart2_ck, eventout adc2_in1, dac1_out1, comp1_inm, comp2_inm, comp3_inm, comp4_inm, comp5_inm, comp6_inm, comp7_inm, opamp4_vinp table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 pinouts and pin description stm32f303xd stm32f303xe 44/184 docid026415 rev 4 21 30 k4 h7 41 pa5 i/o tta (4) tim2_ch1/tim2_etr, tsc_g2_io2, spi1_sck, eventout adc2_in2, dac1_out2, comp1_inm, comp2_inm, comp3_inm, comp4_inm, comp5_inm, comp6_inm, comp7_inm, opamp1_vinp, opamp2_vinm, opamp3_vinp 22 31 l4 h6 42 pa6 i/o tta (4) tim16_ch1, tim3_ch1, tsc_g2_io3, tim8_bkin, spi1_miso, tim1_bkin, comp1_out, eventout adc2_in3, opamp2_vout 23 32 m4 k7 43 pa7 i/o tta - tim17_ch1, tim3_ch2, tsc_g2_io4, tim8_ch1n, spi1_mosi, tim1_ch1n, eventout adc2_in4, comp2_inp, opamp1_vinp, opamp2_vinp 24 33 k5 g6 44 pc4 i/o tta - eventout, tim1_etr, usart1_tx adc2_in5 25 34 l5 f6 45 pc5 i/o tta - eventout, tim15_bkin, tsc_g3_io1, usart1_rx adc2_in11, opamp1_vinm, opamp2_vinm 26 35 m5 j6 46 pb0 i/o tta - tim3_ch3, tsc_g3_io2, tim8_ch2n, tim1_ch2n, eventout adc3_in12, comp4_inp, opamp2_vinp, opamp3_vinp 27 36 m6 k6 47 pb1 i/o tta (4) tim3_ch4, tsc_g3_io3, tim8_ch3n, tim1_ch3n, comp4_out, eventout adc3_in1, opamp3_vout 28 37 l6 k5 48 pb2 i/o tta - tsc_g3_io4, eventout adc2_in12, comp4_inm, opamp3_vinm table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 docid026415 rev 4 45/184 stm32f303xd stm32f303xe pinouts and pin description 67 - - - - 49 pf11 i/o ft (1) eventout, tim20_etr - - - - - 50 pf12 i/o ft (1) eventout, tim20_ch1, fmc_a6 - - - - - 51 vss s - - - - -- - - 52vdd s- (1) -- - - - - 53 pf13 i/o ft (1) eventout, tim20_ch2, fmc_a7 - - - - - 54 pf14 i/o ft (1) eventout, tim20_ch3, fmc_a8 - - - - - 55 pf15 i/o ft (1) eventout, tim20_ch4, fmc_a9 - - - - - 56 pg0 i/o ft (1) eventout, tim20_ch1n, fmc_a10 - - - - - 57 pg1 i/o ft (1) eventout, tim20_ch2n, fmc_a11 - - 38 m7 f8 58 pe7 i/o tta (1) eventout, tim1_etr, fmc_d4 adc3_in13 - 39 l7 e6 59 pe8 i/o tta (1) eventout, tim1_ch1n, fmc_d5 adc34_in6, comp4_inm - 40 m8 - 60 pe9 i/o tta (1) eventout, tim1_ch1, fmc_d6 adc3_in2 - - - - 61 vss s - (1) -- -- - - 62vdd s- (1) -- - 41 l8 - 63 pe10 i/o tta (1) eventout, tim1_ch2n, fmc_d7 adc3_in14 - 42 m9 h5 64 pe11 i/o tta (1) eventout, tim1_ch2, spi4_nss, fmc_d8 adc3_in15 - 43 l9 g5 65 pe12 i/o tta (1) eventout, tim1_ch3n, spi4_sck, fmc_d9 adc3_in16 - 44 m10 - 66 pe13 i/o tta (1) eventout, tim1_ch3, spi4_miso, fmc_d10 adc3_in3 table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 pinouts and pin description stm32f303xd stm32f303xe 46/184 docid026415 rev 4 - 45 m11 - 67 pe14 i/o tta (1) eventout, tim1_ch4, spi4_mosi, tim1_bkin2, fmc_d11 adc4_in1 - 46 m12 - 68 pe15 i/o tta (1) eventout, tim1_bkin, usart3_rx, fmc_d12 adc4_in2 29 47 l10 k4 69 pb10 i/o tta - tim2_ch3, tsc_sync, usart3_tx, eventout comp5_inm, opamp3_vinm, opamp4_vinm 30 48 l11 k3 70 pb11 i/o tta - tim2_ch4, tsc_g6_io1, usart3_rx, eventout adc12_in14, comp6_inp, opamp4_vinp 31 49 f12 k1, j1, k2 71 vss s - - - - 32 50 g12 j5 72 vdd s - - - - 33 51 l12 j4 73 pb12 i/o tta (4) tsc_g6_io2, i2c2_smbal, spi2_nss/i2s2_ws, tim1_bkin, usart3_ck, eventout adc4_in3, comp3_inm, opamp4_vout 34 52 k12 j3 74 pb13 i/o tta - tsc_g6_io3, spi2_sck/i2s2_ck, tim1_ch1n, usart3_cts, eventout adc3_in5, comp5_inp, opamp3_vinp, opamp4_vinp 35 53 k11 j2 75 pb14 i/o tta - tim15_ch1, tsc_g6_io4, spi2_miso/i2s2ext_sd, tim1_ch2n, usart3_rts, eventout adc4_in4, comp3_inp, opamp2_vinp 36 54 k10 h4 76 pb15 i/o tta - rtc_refin, tim15_ch2, tim15_ch1n, tim1_ch3n, spi2_mosi/i2s2_sd, eventout adc4_in5, comp6_inm - 55 k9 - 77 pd8 i/o tta (1) eventout, usart3_tx, fmc_d13 adc4_in12, opamp4_vinm table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 docid026415 rev 4 47/184 stm32f303xd stm32f303xe pinouts and pin description 67 - 56 k8 g4 78 pd9 i/o tta (1) eventout, usart3_rx, fmc_d14 adc4_in13 - 57 j12 h3 79 pd10 i/o tta (1) eventout, usart3_ck, fmc_d15 adc34_in7, comp6_inm - 58 j11 h2 80 pd11 i/o tta (1) eventout, usart3_cts, fmc_a16 adc34_in8, opamp4_vinp - 59 j10 h1 81 pd12 i/o tta (1) eventout, tim4_ch1, tsc_g8_io1, usart3_rts, fmc_a17 adc34_in9 - 60 h12 g3 82 pd13 i/o tta (1) eventout, tim4_ch2, tsc_g8_io2, fmc_a18 adc34_in10, comp5_inm - - - - 83 vss s - (1) -- -- - - 84vdd s- (1) -- - 61 h11 g2 85 pd14 i/o tta (1) eventout, tim4_ch3, tsc_g8_io3, fmc_d0 adc34_in11, opamp2_vinp - 62 h10 g1 86 pd15 i/o tta (1) eventout, tim4_ch4, tsc_g8_io4, spi2_nss, fmc_d1 comp3_inm - - - - 87 pg2 i/o ft (1) eventout, tim20_ch3n, fmc_a12 - - - - - 88 pg3 i/o ft (1) eventout, tim20_bkin, fmc_a13 - - - - - 89 pg4 i/o ft (1) eventout, tim20_bkin2, fmc_a14 - - - - - 90 pg5 i/o ft (1) eventout, tim20_etr, fmc_a15 - - - - - 91 pg6 i/o ft (1) eventout, fmc_int2 - - - - - 92 pg7 i/o ft (1) eventout, fmc_int3 - - - - - 93 pg8 i/o ft (1) eventout - - - - - 94 vss s - (1) -- -- - - 95vdd s- (1) -- table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 pinouts and pin description stm32f303xd stm32f303xe 48/184 docid026415 rev 4 37 63 e12 f4 96 pc6 i/o ft - eventout, tim3_ch1, tim8_ch1, i2s2_mck, comp6_out - 38 64 e11 f2 97 pc7 i/o ft - eventout, tim3_ch2, tim8_ch2, i2s3_mck, comp5_out - 39 65 e10 f1 98 pc8 i/o ft - eventout, tim3_ch3, tim8_ch3, comp3_out - 40 66 d12 f3 99 pc9 i/o ftf - eventout, tim3_ch4, i2c3_sda, tim8_ch4, i2sckin, tim8_bkin2 - 41 67 d11 f5 100 pa8 i/o ftf - mco, i2c3_scl, i2c2_smbal, i2s2_mck, tim1_ch1, usart1_ck, comp3_out, tim4_etr, eventout - 42 68 d10 e5 101 pa9 i/o ftf - i2c3_smbal, tsc_g4_io1, i2c2_scl, i2s3_mck, tim1_ch2, usart1_tx, comp5_out, tim15_bkin, tim2_ch3, eventout - 43 69 c12 e1 102 pa10 i/o ftf - tim17_bkin, tsc_g4_io2, i2c2_sda, spi2_miso/i2s2ext_sd, tim1_ch3, usart1_rx, comp6_out, tim2_ch4, tim8_bkin, eventout - 44 70 b12 e2 103 pa11 i/o ft - spi2_mosi/i2s2_sd, tim1_ch1n, usart1_cts, comp1_out, can_rx, tim4_ch1, tim1_ch4, tim1_bkin2, eventout usb_dm table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 docid026415 rev 4 49/184 stm32f303xd stm32f303xe pinouts and pin description 67 45 71 a12 d1 104 pa12 i/o ft - tim16_ch1, i2sckin, tim1_ch2n, usart1_rts, comp2_out, can_tx, tim4_ch2, tim1_etr, eventout usb_dp 46 72 a11 e3 105 pa13 i/o ft - swdio-jtms, tim16_ch1n, tsc_g4_io3, ir-out, usart3_cts, tim4_ch3, eventout - - - - - 106 ph2 i/o ft (1) eventout - 47 74 f11 a1, a2, b1 107 vss s - - - - 48 75 g11 d2 108 vdd s - - - - 49 76 a10 c2 109 pa14 i/o ftf - swclk-jtck, tsc_g4_io4, i2c1_sda, tim8_ch2, tim1_bkin, usart2_tx, eventout - 50 77 a9 b2 110 pa15 i/o ftf - jtdi, tim2_ch1/tim2_etr, tim8_ch1, tsc_sync, i2c1_scl, spi1_nss, spi3_nss/i2s3_ws, usart2_rx, tim1_bkin, eventout - 51 78 b11 e4 111 pc10 i/o ft - eventout, tim8_ch1n, uart4_tx, spi3_sck/i2s3_ck, usart3_tx - 52 79 c10 d3 112 pc11 i/o ft - eventout, tim8_ch2n, uart4_rx, spi3_miso/i2s3ext_sd, usart3_rx - table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 pinouts and pin description stm32f303xd stm32f303xe 50/184 docid026415 rev 4 53 80 b10 a3 113 pc12 i/o ft - eventout, tim8_ch3n, uart5_tx, spi3_mosi/i2s3_sd, usart3_ck - - 81 c9 b3 114 pd0 i/o ft (1) eventout, can_rx, fmc_d2 - - 82 b9 c3 115 pd1 i/o ft (1) eventout, tim8_ch4, tim8_bkin2, can_tx, fmc_d3 - 54 83 c8 a4 116 pd2 i/o ft - eventout, tim3_etr, tim8_bkin, uart5_rx - - 84 b8 b4 117 pd3 i/o ft (1) eventout, tim2_ch1/tim2_etr, usart2_cts, fmc_clk - - 85 b7 c4 118 pd4 i/o ft (1) eventout, tim2_ch2, usart2_rts, fmc_noe - - 86 a6 - 119 pd5 i/o ft (1) eventout, usart2_tx, fmc_nwe - - - - - 120 vss s - (1) -- -- - - 121vdd s- (1) -- - 87 b6 - 122 pd6 i/o ft (1) eventout, tim2_ch4, usart2_rx, fmc_nwait - - 88 a5 d4 123 pd7 i/o ft (1) eventout, tim2_ch3, usart2_ck, fmc_ne1/fmc_nce2 - - - - - 124 pg9 i/o ft (1) eventout, fmc_ne2/fmc_nce3 - - - - - 125 pg10 i/o ft (1) eventout, fmc_nce4_1/fmc_ne3 - - - - - 126 pg11 i/o ft (1) eventout, fmc_nce4_2 - - - - - 127 pg12 i/o ft (1) eventout, fmc_ne4 - - - - - 128 pg13 i/o ft (1) eventout, fmc_a24 - table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 docid026415 rev 4 51/184 stm32f303xd stm32f303xe pinouts and pin description 67 - - - - 129 pg14 i/o ft (1) eventout, fmc_a25 - - - - - 130 vss s - (1) -- -- - - 131vdd s- (1) -- - - - - 132 pg15 i/o ft (1) eventout - 55 89 a8 a5 133 pb3 i/o ft - jtdo-traceswo, tim2_ch2, tim4_etr, tsc_g5_io1, tim8_ch1n, spi1_sck, spi3_sck/i2s3_ck, usart2_tx, tim3_etr, eventout - 56 90 a7 b5 134 pb4 i/o ft - jtrst, tim16_ch1, tim3_ch1, tsc_g5_io2, tim8_ch2n, spi1_miso, spi3_miso/i2s3ext_sd, usart2_rx, tim17_bkin, eventout - 57 91 c5 a6 135 pb5 i/o ftf - tim16_bkin, tim3_ch2, tim8_ch3n, i2c1_smbal, spi1_mosi, spi3_mosi/i2s3_sd, usart2_ck, i2c3_sda, tim17_ch1, eventout - 58 92 b5 b6 136 pb6 i/o ftf - tim16_ch1n, tim4_ch1, tsc_g5_io3, i2c1_scl, tim8_ch1, tim8_etr, usart1_tx, tim8_bkin2, eventout - 59 93 b4 c5 137 pb7 i/o ftf - tim17_ch1n, tim4_ch2, tsc_g5_io4, i2c1_sda, tim8_bkin, usart1_rx, tim3_ch4, fmc_nadv, eventout - 60 94 a4 a7 138 boot0 i - - - - table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 pinouts and pin description stm32f303xd stm32f303xe 52/184 docid026415 rev 4 61 95 a3 d5 139 pb8 i/o ftf - tim16_ch1, tim4_ch3, tsc_sync, i2c1_scl, usart3_rx, comp1_out, can_rx, tim8_ch2, tim1_bkin, eventout - 62 96 b3 c6 140 pb9 i/o ftf - tim17_ch1, tim4_ch4, i2c1_sda, ir-out, usart3_tx, comp2_out, can_tx, tim8_ch3, eventout - - 97 c3 b7 141 pe0 i/o ft (1) eventout, tim4_etr, tim16_ch1, tim20_etr, usart1_tx, fmc_nbl0 - - 98 a2 a8 142 pe1 i/o ft (1) eventout, tim17_ch1, tim20_ch4, usart1_rx, fmc_nbl1 - 63 99 e3 c7 143 vss s - - - 64 100 c4 a9, a10 , b10 , b8 144 vdd s - - - 1. function availability depends on the chosen device. 2. pc13, pc14 and pc15 are supplied through the power switch. sinc e the switch sinks only a limited amount of current (3 ma), the use of gpio pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as current sources (e.g. to drive an led) after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the ma in reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register descr iption sections in the rm0316 reference manual. 3. the vref+ functionality is not availabl e on the 64-pin package. in this package, the vref+ is internally connected to vdda. 4. these gpios offer a reduced touch sensing sensitivity. it is thus recommended to use t hem as sampling capacitor i/o. table 13. stm32f303xd/e pi n definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions lqfp64 lqfp100 ufbga100 wlcsp100 lqfp144 stm32f303xd stm32f303xe pinouts and pin description docid026415 rev 4 53/184 table 14. stm32f303xd/e alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event port a pa0 - tim2_ ch1/tim 2_etr - tsc_g1 _io1 --- usart2_ cts comp1_ out tim8_ bkin tim8_ etr ---- event out pa1 rtc_ refin tim2_ ch2 - tsc_g1 _io2 --- usart2_ rts - tim15_ ch1n -- - -- event out pa2 - tim2_ ch3 - tsc_g1 _io3 --- usart2_ tx comp2_ out tim15_ ch1 -- - -- event out pa3 - tim2_ ch4 - tsc_g1 _io4 --- usart2_ rx - tim15_ ch2 -- - -- event out pa4 - tim3_ ch2 tsc_g2 _io1 - spi1_nss spi3_nss /i2s3_ws usart2_ ck ------- event out pa5 - tim2_ ch1/tim 2_etr - tsc_g2 _io2 -spi1_sck--------- event out pa6 - tim16_ ch1 tim3_ ch1 tsc_g2 _io3 tim8_bki n spi1_ miso tim1_ bkin - comp1_ out ------ event out pa7 - tim17_ ch1 tim3_ ch2 tsc_g2 _io4 tim8_ch 1n spi1_ mosi tim1_ ch1n -------- event out pa8 mco - - i2c3_ scl i2c2_ smbal i2s2_ mck tim1_ ch1 usart1_ ck comp3_ out - tim4_ etr ---- event out pa9 - - i2c3_ smbal tsc_g4 _io1 i2c2_scl i2s3_ mck tim1_ ch2 usart1_ tx comp5_ out tim15_ bkin tim2_ ch3 ---- event out pinouts and pin description stm32f303xd stm32f303xe 54/184 docid026415 rev 4 port a pa10 - tim17_ bkin - tsc_g4 _io2 i2c2_sda spi2_mis o/i2s2ext _sd tim1_ ch3 usart1_ rx comp6_ out - tim2_ ch4 tim8_b kin --- event out pa11----- spi2_mo si/i2s2_ sd tim1_ ch1n usart1_ cts comp1_ out can_rx tim4_ ch1 tim1_ ch4 tim1_ bkin2 -- event out pa12 - tim16_ ch1 ---i2sckin tim1_ ch2n usart1_ rts comp2_ out can_tx tim4_ ch2 tim1_ etr --- event out pa13 swdio- jtms tim16_ ch1n - tsc_g4 _io3 -ir-out- usart3_ cts -- tim4_ ch3 ---- event out pa14 swclk- jtck -- tsc_g4 _io4 i2c1_sda tim8_ ch2 tim1_ bkin usart2_ tx ------- event out pa15 jtdi tim2_ ch1/tim 2_etr tim8_ ch1 tsc_ sync i2c1_scl spi1_nss spi3_nss /i2s3_ws usart2_ rx - tim1_ bkin -- - -- event out port b pb0 - - tim3_ ch3 tsc_g3 _io2 tim8_ ch2n - tim1_ ch2n -------- event out pb1 - - tim3_ ch4 tsc_g3 _io3 tim8_ ch3n - tim1_ ch3n - comp4_ out ------ event out pb2 - - - tsc_g3 _io4 ----------- event out pb3 jtdo- traces wo tim2_ ch2 tim4_ etr tsc_g5 _io1 tim8_ ch1n spi1_sck spi3_sck /i2s3_ck usart2_ tx -- tim3_ etr ---- event out table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event stm32f303xd stm32f303xe pinouts and pin description docid026415 rev 4 55/184 port b pb4 jtrst tim16_ ch1 tim3_ ch1 tsc_g5 _io2 tim8_ ch2n spi1_ miso spi3_mis o/i2s3ext _sd usart2_ rx -- tim17_ bkin ---- event out pb5 - tim16_ bkin tim3_ ch2 tim8_ ch3n i2c1_ smbal spi1_ mosi spi3_mo si/i2s3_ sd usart2_ ck i2c3_sda - tim17_ ch1 ---- event out pb6 - tim16_ ch1n tim4_ ch1 tsc_g5 _io3 i2c1_scl tim8_ ch1 tim8_ etr usart1_ tx -- tim8_ bkin2 ---- event out pb7 - tim17_ ch1n tim4_ ch2 tsc_g5 _io4 i2c1_sda tim8_ bkin - usart1_ rx -- tim3_ ch4 - fmc_ nadv -- event out pb8 - tim16_ ch1 tim4_ ch3 tsc_ sync i2c1_scl - - usart3_ rx comp1_ out can_rx tim8_ ch2 - tim1_ bkin -- event out pb9 - tim17_ ch1 tim4_ ch4 -i2c1_sda - ir-out usart3_ tx comp2_ out can_tx tim8_ ch3 ---- event out pb10 - tim2_ ch3 - tsc_ sync --- usart3_ tx ------- event out pb11 - tim2_ ch4 - tsc_g6 _io1 --- usart3_ rx ------- event out pb12--- tsc_g6 _io2 i2c2_ smbal spi2_nss /i2s2_ws tim1_ bkin usart3_ ck ------- event out pb13--- tsc_g6 _io3 - spi2_sck /i2s2_ck tim1_ ch1n usart3_ cts ------- event out table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event pinouts and pin description stm32f303xd stm32f303xe 56/184 docid026415 rev 4 port b pb14 - tim15_ ch1 - tsc_g6 _io4 - spi2_mis o/i2s2ext _sd tim1_ ch2n usart3_ rts ------- event out pb15 rtc_ refin tim15_ ch2 tim15_ ch1n - tim1_ ch3n spi2_mo si/i2s2_s d --------- event out port c pc0 - event out tim1_ ch1 ------------- pc1 - event out tim1_ ch2 ------------- pc2 - event out tim1_ ch3 comp7_ out ------------ pc3 - event out tim1_ ch4 -- - tim1_ bkin2 --------- pc4 - event out tim1_ etr -- - - usart1_ tx -------- pc5 - event out tim15_ bkin tsc_g3 _io1 --- usart1_ rx -------- pc6 - event out tim3_ ch1 - tim8_ ch1 - i2s2_ mck comp6_ out -------- pc7 - event out tim3_ ch2 - tim8_ ch2 - i2s3_ mck comp5_ out -------- pc8 - event out tim3_ ch3 - tim8_ ch3 -- comp3_ out -------- pc9 - event out tim3_ ch4 i2c3_ sda tim8_ ch4 i2sckin tim8_ bkin2 --------- table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event stm32f303xd stm32f303xe pinouts and pin description docid026415 rev 4 57/184 port c pc10 - event out -- tim8_ ch1n uart4_ tx spi3_sck /i2s3_ck usart3_ tx -------- pc11 - event out -- tim8_ ch2n uart4_ rx spi3_mis o/i2s3ext _sd usart3_ rx -------- pc12 - event out -- tim8_ ch3n uart5_ tx spi3_mo si/i2s3_ sd usart3_ ck -------- pc13 - event out -- tim1_ ch1n ----------- pc14 - event out -------------- pc15 - event out -------------- port d pd0 - event out - - - - - can_rx - - - - fmc_d2 - - - pd1 - event out -- tim8_ ch4 tim8_ bkin2 can_tx - - - - fmc_d3 - - - pd2 - event out tim3_ etr - tim8_ bkin uart5_ rx ---------- pd3 - event out tim2_ch 1/tim2_ etr -- - - usart2_ cts ---- fmc_ clk -- - pd4 - event out tim2_ ch2 -- - - usart2_ rts ---- fmc_ noe -- - table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event pinouts and pin description stm32f303xd stm32f303xe 58/184 docid026415 rev 4 port d pd5 - event out --- - - usart2_ tx ---- fmc_ nwe -- - pd6 - event out tim2_ ch4 -- - - usart2_ rx ---- fmc_ nwait -- - pd7 - event out tim2_ ch3 -- - - usart2_ ck ---- fmc_ne 1/fmc_ nce2 -- - pd8 - event out --- - - usart3_ tx ---- fmc_ d13 -- - pd9 - event out --- - - usart3_ rx ---- fmc_ d14 -- - pd10 - event out --- - - usart3_ ck ---- fmc_ d15 -- - pd11 - event out --- - - usart3_ cts ---- fmc_ a16 -- - pd12 - event out tim4_ ch1 tsc_g8 _io1 --- usart3_ rts ---- fmc_ a17 -- - pd13 - event out tim4_ ch2 tsc_g8 _io2 -------- fmc_ a18 -- - pd14 - event out tim4_ ch3 tsc_g8 _io3 --------fmc_d0--- pd15 - event out tim4_ ch4 tsc_g8 _io4 - - spi2_nss - - - - - fmc_d1 - - - table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event stm32f303xd stm32f303xe pinouts and pin description docid026415 rev 4 59/184 port e pe0 - event out tim4_ etr - tim16_ ch1 - tim20_ etr usart1_ tx ---- fmc_ nbl0 -- - pe1 - event out -- tim17_ ch1 - tim20_ ch4 usart1_ rx ---- fmc_ nbl1 -- - pe2 traceck event out tim3_ ch1 tsc_g7 _io1 - spi4_sck tim20_ ch1 ----- fmc_ a23 -- - pe3 traced0 event out tim3_ ch2 tsc_g7 _io2 - spi4_nss tim20_ ch2 ----- fmc_ a19 -- - pe4 traced1 event out tim3_ ch3 tsc_g7 _io3 - spi4_nss tim20_ ch1n ----- fmc_ a20 -- - pe5 traced2 event out tim3_ ch4 tsc_g7 _io4 - spi4_ miso tim20_ ch2n ----- fmc_ a21 -- - pe6 traced3 event out --- spi4_ mosi tim20_ ch3n ----- fmc_ a22 -- - pe7 - event out tim1_ etr ---------fmc_d4--- pe8 - event out tim1_ ch1n ---------fmc_d5--- pe9 - event out tim1_ ch1 ---------fmc_d6--- pe10 - event out tim1_ ch2n ---------fmc_d7--- pe11 - event out tim1_ ch2 --spi4_nss------fmc_d8--- table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event pinouts and pin description stm32f303xd stm32f303xe 60/184 docid026415 rev 4 port e pe12 - event out tim1_ ch3n - - spi4_sck - - - - - - fmc_d9 - - - pe13 - event out tim1_ ch3 -- spi4_ miso ------ fmc_ d10 -- - pe14 - event out tim1_ ch4 -- spi4_ mosi tim1_ bkin2 ----- fmc_ d11 -- - pe15 - event out tim1_ bkin -- - - usart3_ rx ---- fmc_ d12 -- - port f pf0 - event out - - i2c2_sda spi2_nss /i2s2_ws tim1_ ch3n --------- pf1 - event out - - i2c2_scl spi2_sck /i2s2_ck ---------- pf2 - event out tim20_ ch3 ---------fmc_a2--- pf3 - event out tim20_ ch4 ---------fmc_a3--- pf4 - event out comp1_ out tim20_ ch1n --------fmc_a4--- pf5 - event out tim20_ ch2n ---------fmc_a5--- pf6 - event out tim4_ ch4 - i2c2_scl - - usart3_ rts ---- fmc_ niord -- - pf7 - event out tim20_ bkin --------- fmc_ nreg -- - table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event stm32f303xd stm32f303xe pinouts and pin description docid026415 rev 4 61/184 port f pf8 - event out tim20_ bkin2 --------- fmc_ niowr -- - pf9 - event out tim20_ bkin tim15_ ch1 - spi2_sck - - - - - - fmc_cd - - - pf10 - event out tim20_ bkin2 tim15_ ch2 -spi2_sck------ fmc_ intr -- - pf11 - event out tim20_ etr ------------- pf12 - event out tim20_ ch1 ---------fmc_a6--- pf13 - event out tim20_ ch2 ---------fmc_a7--- pf14 - event out tim20_ ch3 ---------fmc_a8--- pf15 - event out tim20_ ch4 ---------fmc_a9--- port g pg0 - event out tim20_ ch1n --------- fmc_ a10 -- - pg1 - event out tim20_ ch2n --------- fmc_ a11 -- - pg2 - event out tim20_ ch3n --------- fmc_ a12 -- - pg3 - event out tim20_ bkin --------- fmc_ a13 -- - pg4 - event out tim20_ bkin2 --------- fmc_ a14 -- - table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event pinouts and pin description stm32f303xd stm32f303xe 62/184 docid026415 rev 4 port g pg5 - event out tim20_ etr --------- fmc_ a15 -- - pg6 - event out ---------- fmc_ int2 -- - pg7 - event out ---------- fmc_ int3 -- - pg8 - event out -------------- pg9 - event out ---------- fmc_ne 2/fmc_ nce3 -- - pg10 - event out ---------- fmc_ nce4_1/ fmc_ ne3 -- - pg11 - event out ---------- fmc_ nce4_2 -- - pg12 - event out ---------- fmc_ ne4 -- - pg13 - event out ---------- fmc_ a24 -- - pg14 - event out ---------- fmc_ a25 -- - pg15 - event out -------------- table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event stm32f303xd stm32f303xe pinouts and pin description docid026415 rev 4 63/184 port h ph0 - event out tim20_ ch1 ---------fmc_a0--- ph1 - event out tim20_ ch2 ---------fmc_a1--- ph2 - event out -------------- table 14. stm32f303xd/e alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim2/15/ 16/17/e vent i2c3/tim1 /2/3/4/8/20 /15/gpco mp1 i2c3/tim 8/20/15/g pcomp7 /tsc i2c1/2/ti m1/8/16/1 7 spi1/spi2 /i2s2/spi3 /i2s3/spi4 /uart4/5/ tim8/infra red spi2/i2s2/ spi3/i2s3/ tim1/8/20/ infrared usart1/ 2/3/can/ gpcomp 3/5/6 i2c3/gpc omp1/2/3/ 4/5/6 can/tim1 /8/15 tim2/3/ 4/8/17 tim1/8 sdio/fs mc/tim1 - - event memory mapping stm32f303xd stm32f303xe 64/184 docid026415 rev 4 5 memory mapping figure 9. stm32f303xd/e memory map [ ) ) ) ) ) ) ) ) [ ( [ & [ $ [ [ [ [ [ & r u w h [ 0 z l w k ) 3 8 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 & 2 ' ( 2 s w l r q e \ w h v 6 \ v w h p p h p r u \ & & 0 5 $ 0 ) o d v k p h p r u \ ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q $ + % $ + % $ 3 % $ 3 % [ [ [ [ ) ) [ [ & [ [ $ [ [ ) ) ) ) ) ) ) [ ) ) ) ) [ ) ) ) ' [ [ [ [ [ [ 5 h v h u y h g 0 6 y 9 $ + % [ ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g ) 0 & e d q n d q g e d q n ) 0 & e d q n d q g e d q n [ $ ) 0 & f r q w u r o u h j l v w h u v docid026415 rev 4 65/184 stm32f303xd stm32f303xe memory mapping 67 table 15. memory map, peripheral register boundary addresses bus boundary address size (bytes) peripheral ahb4 0xa000 0000 - 0xa000 0fff 4 k fsmc control registers 0x8000 0000 - 0x9fff ffff 512 m fsmc banks 3 and 4 0x6000 0000 - 0x7fff ffff 512 m fsmc banks 1 and 2 0x5000 0800 - 0x5fff ffff 384 m reserved ahb3 0x5000 0400 - 0x5000 07ff 1 k adc3 - adc4 0x5000 0000 - 0x5000 03ff 1 k adc1 - adc2 0x4800 2000 - 0x4fff ffff ~132 m reserved ahb2 0x4800 1c00 - 0x4800 1fff 1 k gpioh 0x4800 1800 - 0x4800 1bff 1 k gpiog 0x4800 1400 - 0x4800 17ff 1 k gpiof 0x4800 1000 - 0x4800 13ff 1 k gpioe 0x4800 0c00 - 0x4800 0fff 1 k gpiod 0x4800 0800 - 0x4800 0bff 1 k gpioc 0x4800 0400 - 0x4800 07ff 1 k gpiob 0x4800 0000 - 0x4800 03ff 1 k gpioa 0x4002 4400 - 0x47ff ffff ~128 m reserved ahb1 0x4002 4000 - 0x4002 43ff 1 k tsc 0x4002 3400 - 0x4002 3fff 3 k reserved 0x4002 3000 - 0x4002 33ff 1 k crc 0x4002 2400 - 0x4002 2fff 3 k reserved 0x4002 2000 - 0x4002 23ff 1 k flash interface 0x4002 1400 - 0x4002 1fff 3 k reserved 0x4002 1000 - 0x4002 13ff 1 k rcc 0x4002 0800 - 0x4002 0fff 2 k reserved 0x4002 0400 - 0x4002 07ff 1 k dma2 0x4002 0000 - 0x4002 03ff 1 k dma1 memory mapping stm32f303xd stm32f303xe 66/184 docid026415 rev 4 0x4001 8000 - 0x4001 ffff 32 k reserved 0x4001 5400 - 0x4001 7fff 11 k reserved 0x4001 5000 - 0x4001 53ff 1 k tim20 0x4001 4c00 - 0x4001 4fff 1 k reserved 0x4001 4800 - 0x4001 4bff 1 k tim17 0x4001 4400 - 0x4001 47ff 1 k tim16 0x4001 4000 - 0x4001 43ff 1 k tim15 0x4001 3c00 - 0x4001 3fff 1 k spi4 0x4001 3800 - 0x4001 3bff 1 k usart1 0x4001 3400 - 0x4001 37ff 1 k tim8 0x4001 3000 - 0x4001 33ff 1 k spi1 0x4001 2c00 - 0x4001 2fff 1 k tim1 0x4001 0800 - 0x4001 2bff 9 k reserved 0x4001 0400 - 0x4001 07ff 1 k exti 0x4001 0000 - 0x4001 03ff 1 k syscfg + comp + opamp 0x4000 7c00 - 0x4000 ffff 32 k reserved table 15. memory map, peripheral register boundary addresses (continued) bus boundary address size (bytes) peripheral docid026415 rev 4 67/184 stm32f303xd stm32f303xe memory mapping 67 apb1 0x4000 7800 - 0x4000 7bff 1 k i2c3 0x4000 7400 - 0x4000 77ff 1 k dac 0x4000 7000 - 0x4000 73ff 1 k pwr 0x4000 6800 - 0x4000 6fff 2 k reserved 0x4000 6400 - 0x4000 67ff 1 k bxcan 0x4000 6000 - 0x4000 63ff 1 k usb/can sram 0x4000 5c00 - 0x4000 5fff 1 k usb device fs 0x4000 5800 - 0x4000 5bff 1 k i2c2 0x4000 5400 - 0x4000 57ff 1 k i2c1 0x4000 5000 - 0x4000 53ff 1 k uart5 0x4000 4c00 - 0x4000 4fff 1 k uart4 0x4000 4800 - 0x4000 4bff 1 k usart3 0x4000 4400 - 0x4000 47ff 1 k usart2 0x4000 4000 - 0x4000 43ff 1 k i2s3ext 0x4000 3c00 - 0x4000 3fff 1 k spi3/i2s3 0x4000 3800 - 0x4000 3bff 1 k spi2/i2s2 0x4000 3400 - 0x4000 37ff 1 k i2s2ext 0x4000 3000 - 0x4000 33ff 1 k iwdg 0x4000 2c00 - 0x4000 2fff 1 k wwdg 0x4000 2800 - 0x4000 2bff 1 k rtc 0x4000 1800 - 0x4000 27ff 4 k reserved 0x4000 1400 - 0x4000 17ff 1 k tim7 0x4000 1000 - 0x4000 13ff 1 k tim6 0x4000 0c00 - 0x4000 0fff 1 k reserved 0x4000 0800 - 0x4000 0bff 1 k tim4 0x4000 0400 - 0x4000 07ff 1 k tim3 0x4000 0000 - 0x4000 03ff 1 k tim2 table 15. memory map, peripheral register boundary addresses (continued) bus boundary address size (bytes) peripheral electrical characteristics stm32f303xd stm32f303xe 68/184 docid026415 rev 4 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 2.0 to 3.6 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 10. pin loading conditions figure 11. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid026415 rev 4 69/184 stm32f303xd stm32f303xe electrical characteristics 161 6.1.6 power supply scheme figure 12. power supply scheme 1. dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins. caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 0 6 9 / h y h o v k l i w h u $ q d o r j 5 & v 3 / / f r p s d u d w r u v 2 3 $ 0 3 3 r z h u v z l w f k $ ' & ' $ & . h u q h o o r j l f & 3 8 g l j l w d o p h p r u l h v , 2 o r j l f % d f n x s f l u f x l w u \ / 6 ( 5 7 & : d n h x s o r j l f % d f n x s u h j l v w h u v 9 % $ 7 9 * 3 , 2 v 9 ' ' 2 8 7 , 1 5 h j x o d w r u [ 9 ' ' [ 9 6 6 9 ' ' $ 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 6 6 $ [ q ) [ ? ) q ) ? ) q ) ? ) 9 5 ( ) electrical characteristics stm32f303xd stm32f303xe 70/184 docid026415 rev 4 6.1.7 current consumption measurement figure 13. current consum ption measurement scheme - 3 6 6 $ $ 6 $ $ ! ) $ $ ) $ $ ! docid026415 rev 4 71/184 stm32f303xd stm32f303xe electrical characteristics 161 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 16: voltage characteristics , table 17: current characteristics , and table 18: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 16. voltage characteristics (1) symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda, v bat and v dd ) -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda -0.4 v ref+ ?v dda (2) allowed voltage difference for v ref+ > v dda -0.4 v in (3) input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 v input voltage on tta pins v ss ? 0.3 4.0 input voltage on any other pin v ss ? 0.3 4.0 input voltage on boot0 pin 0 9 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.13: electrical sensitivity characteristics - 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. the following relationship must be respected between v dda and v dd : v dda must power on before or at the same time as v dd in the power up sequence. v dda must be greater than or equal to v dd . 2. v ref+ must be always lower or equal than v dda (v ref+ v dda) . if unused then it must be connected to v dda . 3. v in maximum must always be respected. refer to table 17: current characteristics for the maximum allowed injected current values. electrical characteristics stm32f303xd stm32f303xe 72/184 docid026415 rev 4 table 17. current characteristics symbol ratings max. unit i vdd total current into sum of all vdd_x power lines (source) 160 ma i vss total current out of sum of all vss_x ground lines (sink) -160 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss _x ground line (sink) (1) 100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) -80 i inj(pin) injected current on ft, ftf, and b pins (3) -5/+0 injected current on tc and rst pin (4) 5 injected current on tta pins (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (v dd , v dda ) and ground (v ss and v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins.the total output current must not be sunk/sourced between two c onsecutive power supply pins referrin g to high pin count lqfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 16: voltage characteristics for the maximum allowed input voltage values. 5. a positive injection is induced by v in > v dda while a negative injection is induced by v in < v ss . i inj (pin) must never be exceeded. refer also to table 16: voltage characteristics for the maximum allowed input voltage values. negative injection disturbs the analog performance of the device. see note (2) below table 80 . 6. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 18. thermal characteristics symbol ratings value unit t stg storage temperature range -65 to +150 c t j maximum junction temperature 150 c docid026415 rev 4 73/184 stm32f303xd stm32f303xe electrical characteristics 161 6.3 operating conditions 6.3.1 general operating conditions table 19. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 72 mhz f pclk1 internal apb1 clock frequency - 0 36 f pclk2 internal apb2 clock frequency - 0 72 v dd standard operating voltage - 2 3.6 v v dda analog operating voltage (opamp and dac not used) must have a potential equal to or higher than v dd 23.6 v analog operating voltage (opamp and dac used) 2.4 3.6 v bat backup operating voltage - 1.65 3.6 v v in i/o input voltage tc i/o -0.3 v dd +0.3 v tta i/o -0.3 v dda +0.3 ft and ftf i/o (1) 1. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. -0.3 5.5 boot0 0 5.5 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see section 7.6: thermal characteristics ). lqfp144 - 606 mw wlcsp100 - 454 lqfp100 - 476 ufbga100 - 339 lqfp64 - 435 t a ambient temperature for 6 suffix version maximum power dissipation -40 85 c low power dissipation (3) 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.6: thermal characteristics ). -40 105 ambient temperature for 7 suffix version maximum power dissipation -40 105 c low power dissipation (3) -40 125 t j junction temperature range 6 suffix version -40 105 c 7 suffix version -40 125 electrical characteristics stm32f303xd stm32f303xe 74/184 docid026415 rev 4 6.3.2 operating conditions at power-up / power-down the parameters given in table 20 are derived from tests performed under the ambient temperature condition summarized in table 19 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 21 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . table 20. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 20 t vdda v dda rise time rate - 0 v dda fall time rate 20 table 21. embedded reset and power control block characteristics symbol parameter conditions min. typ. max. unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (1) pdr hysteresis - - 40 - mv docid026415 rev 4 75/184 stm32f303xd stm32f303xe electrical characteristics 161 table 22. programmable voltage detector characteristics symbol parameter conditions min (1) 1. data based on characterization results only, not tested in production. typ max (1) unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 falling edge 2.09 2.18 2.27 v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 falling edge 2.18 2.28 2.38 v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 falling edge 2.28 2.38 2.48 v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 falling edge 2.37 2.48 2.59 v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 falling edge 2.47 2.58 2.69 v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 falling edge 2.56 2.68 2.8 v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 falling edge 2.66 2.78 2.9 v pvdhyst (2) 2. guaranteed by design, not tested in production. pvd hysteresis - - 100 - mv idd(pvd) pvd current consumption - - 0.15 0.26 a electrical characteristics stm32f303xd stm32f303xe 76/184 docid026415 rev 4 6.3.4 embedded reference voltage the parameters given in table 23 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 13: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. note: the total current consumption is the sum of i dd and i dda . table 23. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint adc sampling time when reading the internal reference voltage -2.2--s v rerint internal reference voltage spread over the temperature range v dd = 3 v 10 mv - - 10 (2) 2. guaranteed by design, not tested in production. mv t coeff temperature coefficient - - - 100 (2) ppm/c table 24. internal reference voltage calibration values calibration value name description memory address v refint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb docid026415 rev 4 77/184 stm32f303xd stm32f303xe electrical characteristics 161 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz,1 wait state from 24 to 48 mhz and 2 wait states from 48 to 72 mhz) ? prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk2 = f hclk and f pclk1 = f hclk/2 ? when f hclk > 8 mhz, the pll is on and the pll input is equal to hsi/2 (4 mhz) or hse (8 mhz) in bypass mode. the parameters given in table 25 to table 29 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 19 . electrical characteristics stm32f303xd stm32f303xe 78/184 docid026415 rev 4 table 25. typical and maximum current consumption from v dd supply at v dd = 3.6v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, executing from flash external clock (hse bypass) 72 mhz 66.4 76.5 76.9 77.4 33.0 37.2 38.1 38.9 ma 64 mhz 59.8 66.4 67.7 68.6 29.7 33.5 34.3 35.0 48 mhz 47.3 53.7 53.8 55.1 23.2 26.2 27.1 28.0 32 mhz 33.3 36.8 37.4 38.5 16.8 19.8 20.6 21.4 24 mhz 26.0 29.4 30.0 31.2 13.5 16.6 17.4 18.6 8 mhz 10.7 13.8 14.4 15.3 6.63 10.2 10.5 11.2 1 mhz 4.27 7.47 8.13 8.90 3.78 7.40 7.70 8.50 internal clock (hsi) 64 mhz 55.6 59.6 62.8 63.2 29.4 33.1 34.5 35.0 48 mhz 43.6 47.0 49.2 50.1 23.1 26.2 27.1 28.0 32 mhz 30.8 33.6 35.3 35.8 16.7 19.8 20.6 21.5 24 mhz 24.0 28.0 28.2 29.7 13.5 16.5 17.5 18.4 8 mhz 10.5 13.6 14.7 15.2 6.63 9.74 10.6 11.2 i dd supply current in run mode, executing from ram external clock (hse bypass) 72 mhz 66.2 76.2 (2) 76.7 77.2 (2) 32.8 36.9 (2) 37.7 38.5 (2) 64 mhz 59.6 66.2 67.6 68.4 29.3 33.1 33.9 34.4 48 mhz 47.0 53.4 53.6 54.9 22.4 25.6 26.2 27.2 32 mhz 33.0 36.6 37.2 38.1 16.0 19.0 19.5 20.4 24 mhz 25.6 29.0 29.5 30.6 12.8 15.7 16.3 17.6 8 mhz 10.3 13.4 13.8 14.7 6.40 9.48 9.93 10.90 1 mhz 3.92 7.06 7.54 8.60 3.42 6.53 7.05 8.10 internal clock (hsi) 64 mhz 55.4 59.2 62.5 62.9 29.1 32.7 34.0 34.6 48 mhz 43.1 46.7 49.0 49.9 22.8 26.1 26.8 27.8 32 mhz 30.5 33.2 35.0 35.5 15.8 18.8 19.5 20.9 24 mhz 23.8 27.8 27.9 29.2 12.6 15.6 16.3 17.5 8 mhz 9.85 13.1 14.1 14.6 6.20 9.37 10.3 10.7 docid026415 rev 4 79/184 stm32f303xd stm32f303xe electrical characteristics 161 i dd supply current in sleep mode, executing from flash or ram external clock (hse bypass) 72 mhz 48.8 53.5 (2) 53.6 54.0 (2) 7.60 8.20 (2) 8.50 9.00 (2) ma 64 mhz 43.5 48.6 49.1 49.3 6.90 7.50 7.80 8.00 48 mhz 33.6 38.1 40.0 41.3 5.30 5.80 6.00 6.40 32 mhz 24.3 27.5 28.1 29.3 3.80 4.10 4.40 4.70 24 mhz 18.6 21.9 22.4 22.6 2.90 3.30 3.40 3.90 8 mhz 8.24 11.27 11.79 12.70 1.36 1.74 1.85 2.00 1 mhz 3.64 6.72 7.36 8.30 0.79 1.17 1.26 1.35 internal clock (hsi) 64 mhz 39.7 43.9 45.5 45.8 6.70 7.30 7.40 7.70 48 mhz 30.4 33.9 35.3 36.5 5.10 5.60 5.70 6.10 32 mhz 21.9 25.8 26.2 26.7 3.60 4.10 4.20 4.50 24 mhz 17.0 20.2 21.5 21.7 2.98 3.41 3.46 3.57 8 mhz 7.81 11.0 11.7 12.4 1.41 1.74 1.81 1.87 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and test ed in production with code executing from ram. table 25. typical and maximum current consumption from v dd supply at v dd = 3.6v (continued) symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c table 26. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run mode, code executing from flash or ram hse bypass 72 mhz 220 243 255 260 241 264 281 287 a 64 mhz 194 215 226 231 212 233 248 254 48 mhz 145 164 172 176 158 176 187 192 32 mhz 100 116 121 124 108 123 130 134 24 mhz 78 92 96 98 85 97 102 105 8 mhz 1.9 3.1 3.6 4.4 2.5 3.7 4.4 5.5 1 mhz 1.9 3.1 3.6 4.4 2.5 3.7 4.4 5.5 hsi clock 64 mhz 266 290 301 306 295 320 335 341 48 mhz 216 237 247 251 240 262 274 279 32 mhz 170 188 196 199 190 208 217 221 24 mhz 148 164 170 172 166 182 189 192 8 mhz 70 78 81 82 84 92 95 97 1. current consumption from the v dda supply is independent of whether the peripherals are on or off. furthermore when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production. electrical characteristics stm32f303xd stm32f303xe 80/184 docid026415 rev 4 table 27. typical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd =v dda )max unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 18.4 18.7 18.8 18.9 19.0 19.1 47 435 940 a regulator in low-power mode, all oscillators off 6.80 6.94 7.11 7.18 7.26 7.39 33 408 898 supply current in standby mode lsi on and iwdg on 0.72 0.87 0.99 1.10 1.23 1.37 - - - lsi off and iwdg off 0.57 0.68 0.76 0.85 0.94 1.03 6.2 8.6 13.5 table 28. typical and maximum v dda consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda )max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply current in stop mode v dda supervisor on regulator in run/low- power mode, all oscillators off 1.72 1.85 1.97 2.10 2.25 2.41 10.7 11 12 a supply current in standby mode lsi on and iwdg on 2.08 2.26 2.43 2.61 2.82 3.05 - - - lsi off and iwdg off 1.60 1.73 1.85 1.98 2.13 2.29 3.6 4 6 supply current in stop mode v dda supervisor off regulator in run/low- power mode, all oscillators off 1.00 1.02 1.05 1.10 1.16 1.24 - - - supply current in standby mode lsi on and iwdg on 1.36 1.43 1.51 1.61 1.74 1.88 - - - lsi off and iwdg off 0.88 0.90 0.93 0.98 1.05 1.12 - - - 1. data based on characterization results, not tested in production. docid026415 rev 4 81/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 14. typical v bat current consumption (lse and rtc on/lsedrv[1:0] 00?) table 29. typical and maximum current consumption from v bat supply symbol para meter conditions (1) typ @v bat max @v bat = 3.6 v (2) unit 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v t a = 25c t a = 85c t a = 105c i dd_vbat backup domain supply current lse & rtc on; ?xtal mode? lower driving capability; lsedrv[1: 0] = '00' 0.48 0.50 0.52 0.58 0.65 0. 72 0.80 0.90 1.1 1.5 2.0 a lse & rtc on; ?xtal mode? higher driving capability; lsedrv[1: 0] = '11' 0.83 0.86 0.90 0.98 1.03 1. 10 1.20 1.30 1.5 2.2 2.9 1. crystal used: abracon abs07-120-32.768 khz-t with a cl of 6 pf for typical values. 2. data based on characterization re sults, not tested in production. ? # ? # ? # ? # 6 6 6 6 6 6 6 6 4 ! ? # ? ! ) 6 " ! 4 - 3 6 electrical characteristics stm32f303xd stm32f303xe 82/184 docid026415 rev 4 typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins available on each packag e are in analog input configuration ? the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz), and flash prefetch is on ? when the peripherals are enabled, f apb1 = f ahb/2 , f apb2 = f ahb ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 mhz, 2 mhz, 1 mhz, 500 khz and 125 khz respectively. table 30. typical current consumption in r un mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 72 mhz 60.7 27.3 ma 64 mhz 54.3 24.1 48 mhz 42.1 19.4 32 mhz 28.7 13.9 24 mhz 22.2 11.0 16 mhz 15.4 7.9 8 mhz 8.3 4.51 4 mhz 5.14 3.02 2 mhz 3.37 2.21 1 mhz 2.49 1.80 500 khz 2.04 1.57 125 khz 1.71 0.84 i dda (1) (2) supply current in run mode from v dda supply 72 mhz 239.7 a 64 mhz 210.5 48 mhz 155.6 32 mhz 105.5 24 mhz 81.9 16 mhz 58.6 8 mhz 1.16 4 mhz 1.16 2 mhz 1.16 1 mhz 1.16 500 khz 1.16 125 khz 1.16 1. v dda supervisor is off. 2. when peripherals are enabled, the power consumption of the anal og part of peripherals such as adc, dac, comparators, opamp is not included. refer to the tables of characteristics in the subsequent sections. docid026415 rev 4 83/184 stm32f303xd stm32f303xe electrical characteristics 161 table 31. typical current consumption in sl eep mode, code running from flash or ram symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 72 mhz 43.0 7.4 ma 64 mhz 38.3 6.8 48 mhz 29.0 5.29 32 mhz 19.7 3.91 24 mhz 15.2 3.19 16 mhz 10.8 2.46 8 mhz 5.85 1.55 4 mhz 3.80 1.45 2 mhz 2.67 1.32 1 mhz 2.12 1.22 500 khz 1.83 1.19 125 khz 1.60 0.83 i dda (1) (2) supply current in sleep mode from v dda supply 72 mhz 239.7 a 64 mhz 210.5 48 mhz 155.6 32 mhz 105.5 24 mhz 81.9 16 mhz 58.6 8 mhz 1.16 4 mhz 1.16 2 mhz 1.16 1 mhz 1.16 500 khz 1.16 125 khz 1.16 1. v dda supervisor is off. 2. when peripherals are enabled, the power consumption of the anal og part of peripherals such as adc, dac, comparators, opamp is not included. refer to the tables of characteristics in the subsequent sections. electrical characteristics stm32f303xd stm32f303xe 84/184 docid026415 rev 4 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 65: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 33: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext +c s the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = docid026415 rev 4 85/184 stm32f303xd stm32f303xe electrical characteristics 161 table 32. switching output i/o current consumption symbol parameter conditions (1) 1. cs = 5 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.90 ma 4 mhz 0.93 8 mhz 1.16 18 mhz 1.60 36 mhz 2.51 48 mhz 2.97 v dd = 3.3 v c ext = 10 pf c = c int + c ext +c s 2 mhz 0.93 4 mhz 1.06 8 mhz 1.47 18 mhz 2.26 36 mhz 3.39 48 mhz 5.99 v dd = 3.3 v c ext = 22 pf c = c int + c ext +c s 2 mhz 1.03 4 mhz 1.30 8 mhz 1.79 18 mhz 3.01 36 mhz 5.99 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 1.10 4 mhz 1.31 8 mhz 2.06 18 mhz 3.47 36 mhz 8.35 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s 2 mhz 1.20 4 mhz 1.54 8 mhz 2.46 18 mhz 4.51 36 mhz 9.98 electrical characteristics stm32f303xd stm32f303xe 86/184 docid026415 rev 4 on-chip peripheral current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input configuration ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature at 25c and v dd = v dda = 3.3 v. docid026415 rev 4 87/184 stm32f303xd stm32f303xe electrical characteristics 161 table 33. peripheral current consumption peripheral typical consumption (1) unit i dd busmatrix (2) 8.3 a/mhz dma1 7.0 dma2 5.4 fsmc 35.0 crc 1.5 gpioh 1.3 gpioa 5.4 gpiob 5.3 gpioc 5.4 gpiod 5.0 gpioe 5.4 gpiof 5.2 gpiog 5.0 tsc 5.2 adc1&2 15.4 adc3&4 16.2 apb2-bridge (3) 3.1 syscfg 4.0 tim1 26.0 spi1 6.2 tim8 26.4 usart1 17.7 spi4 6.2 tim15 11.9 tim16 8.0 tim17 8.5 tim20 25.3 electrical characteristics stm32f303xd stm32f303xe 88/184 docid026415 rev 4 apb1-bridge (3) 6.7 a/mhz tim2 39.2 tim3 30.8 tim4 31.3 tim6 4.3 tim7 4.3 wwdg 1.3 spi2 33.6 spi3 33.9 usart2 39.3 usart3 39.3 uart4 29.8 uart5 27.0 i2c1 6.7 i2c2 6.4 usb 14.7 can 25.6 pwr 3.7 dac 22.1 i2c3 6.8 1. the power consumption of the analog part (i dda ) of peripherals such as adc, dac, comparators, opamp is not included. refer to the tables of characteristics in the subsequent sections. 2. busmatrix is automatically active when at least one master is on (cpu, dma1 or dma2). 3. the apbx bridge is automatically active when at least one peripheral is on on the same bus. table 33. peripheral current consumption (continued) peripheral typical consumption (1) unit i dd docid026415 rev 4 89/184 stm32f303xd stm32f303xe electrical characteristics 161 6.3.6 wakeup time from low-power mode the wakeup times given in table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep mode: the wakeup event is wfe. ? wkup1 (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . table 34. low-power mode wakeup timings symbol parameter conditions typ @v dd, v dd = v dda max unit 2.0 v 2.4 v 2.7 v 3 v 3.3 v 3.6 v t wustop wakeup from stop mode regulator in run mode 5.4 5.2 5.2 5.1 5.0 4.9 5.6 s regulator in low power mode 12.0 10.1 9.2 8.6 8.1 7.8 12.9 t wustandby (1) wakeup from standby mode lsi and iwdg off 91.0 77.1 71.7 68.0 65.1 63.1 139 t wusleep wakeup from sleep mode -6- cpu clock cycles 1. data based on characterization results, not tested in production. electrical characteristics stm32f303xd stm32f303xe 90/184 docid026415 rev 4 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillato r is switched off and the inpu t pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.15 . however, the recommended clock input waveform is shown in figure 15 . figure 15. high-speed external clock source ac timing diagram table 35. high-speed external user clock characteristics symbol parameter condi tions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 1832mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hseh) t w(hsel) osc_in high or low time (1) 15 - - ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / docid026415 rev 4 91/184 stm32f303xd stm32f303xe electrical characteristics 161 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.15 . however, the recommended clock input waveform is shown in figure 16 figure 16. low-speed external clock source ac timing diagram table 36. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lseh) t w(lsel) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / electrical characteristics stm32f303xd stm32f303xe 92/184 docid026415 rev 4 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 37 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). table 37. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min (2) 2. guaranteed by design, not tested in production. typ max (2) unit f osc_in oscillator frequency - 4 8 32 mhz r f feedback resistor - - 200 k i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time. --8.5 ma v dd = 3.3 v, rm= 30 , cl=10 pf@8 mhz -0.4- v dd = 3.3 v, rm= 45 , cl=10 pf@8 mhz -0.5- v dd = 3.3 v, rm= 30 , cl=5 pf@32 mhz -0.8- v dd = 3.3 v, rm= 30 , cl=10 pf@32 mhz -1- v dd = 3.3 v, rm= 30 , cl=20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms docid026415 rev 4 93/184 stm32f303xd stm32f303xe electrical characteristics 161 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 17 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 17. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 5 ) % l d v f r q w u r o o h g j d l q i + 6 ( 5 ( ; 7 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics stm32f303xd stm32f303xe 94/184 docid026415 rev 4 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 38 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . table 38. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.50.9 a lsedrv[1:0]=01 medium low driving capability --1 lsedrv[1:0]=10 medium high driving capability --1.3 lsedrv[1:0]=11 higher driving capability --1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]=01 medium low driving capability 8- - lsedrv[1:0]=10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is ena bled (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer. docid026415 rev 4 95/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 18. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics stm32f303xd stm32f303xe 96/184 docid026415 rev 4 6.3.8 internal clock source characteristics the parameters given in table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 19 . high-speed internal (hsi) rc oscillator figure 19. hsi oscillator accuracy characterization results for soldered parts table 39. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 8 - mhz trim hsi user trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle - 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator t a = -40 to 105c -2.8 (3) 3. data based on characterization results, not tested in production. -3.8 (3) % t a = -10 to 85c -1.9 (3) -2.3 (3) t a = 0 to 85c -1.9 (3) -2 (3) t a = 0 to 70c -1.3 (3) -2 (3) t a = 0 to 55c -1 (3) -2 (3) t a = 25c (4) 4. factory calibrated, parts not soldered. -1 - 1 t su(hsi) hsi oscillator startup time - 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption -80100 (2) a 0 6 9 5 < ? $ > " . " 9 . * / docid026415 rev 4 97/184 stm32f303xd stm32f303xe electrical characteristics 161 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 19 . table 40. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dd(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 41. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 1 (2) -24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -72mhz t lock pll lock time - - 200 (2) s jitter cycle-to-cycle jitter - - 300 (2) 2. guaranteed by design, not tested in production. ps electrical characteristics stm32f303xd stm32f303xe 98/184 docid026415 rev 4 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. 6.3.11 fsmc characteristics unless otherwise specified, the parameters given in table 44 to table 59 for the fsmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage conditions summarized in table 19 with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5vdd refer to section 6.3.15: i/o port characteristics : for more details on the input/output characteristics. table 42. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +105 c 40 53.5 60 s t erase page (2 kb) erase time t a = ?40 to +105 c 20 - 40 ms t me mass erase time t a = ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 43. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. data based on characterization results, not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycle (2) at t a = 55 c 20 docid026415 rev 4 99/184 stm32f303xd stm32f303xe electrical characteristics 161 asynchronous waveforms and timings figure 20 to figure 23 represent asynchronous waveforms and table 44 to table 51 provide the corresponding timings. the result s shown in these tables are obtained with the following fsmc configuration: ? addresssetuptime = 0x1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 (except for asynchronous nwait mode, datasetuptime = 0x5) ? busturnaroundduration = 0x0 ? nor nwait pulse width= 1thclk in all the timing tables, the t hclk is the hclk clock period. figure 20. asynchronous non-multiple xed sram/psram/nor read timings $ a t a & - # ? . % & - # ? . " , ; = & - # ? $ ; = t v " , ? . % t h $ a t a ? . % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % & - # ? . 7 % t s u $ a t a ? . % t w . % - 3 6 w . / % t t v . / % ? . % t h . % ? . / % t h $ a t a ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 electrical characteristics stm32f303xd stm32f303xe 100/184 docid026415 rev 4 table 44. asynchronous non-multiplexed sram/psram/nor read timings (1) 1. based on characterization, not tested in production symbol parameter min max unit t w(ne) fmc_ne low time 2thclk? 1 2thclk+1 ns t v(noe_ne) fmc_nex low to fmc_noe low 0 1 t w(noe) fmc_noe low time 2thclk 2thclk+ 1.5 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0.5 - t v(a_ne) fmc_nex low to fmc_a valid - 3 t h(a_noe) address hold time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 (na) t h(bl_noe) fmc_bl hold time after fmc_noe high 0 - t su(data_ne) data to fmc_nex high setup time thclk + 6 - t su(data_noe) data to fmc_noex high setup time thclk +7 - t h(data_noe) data hold time after fmc_noe high 0 - t h(data_ne) data hold time after fmc_nex high 0 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 2 t w(nadv) fmc_nadv low time - thclk +1.5 table 45. asynchronous non-multiplexed sram/psram/nor read-nwait timings (1) 1. based on characterization, not tested in production symbol parameter min max unit t w(ne) fmc_ne low time 7thclk +0.5 7thclk+ 1 ns t w(noe) fmc_nwe low time 6thclk -1.5 6thclk +2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 4thclk +5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4thclk-3 - docid026415 rev 4 101/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 21. asynchronous non-multiplexed sram/psram/nor write timings 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. table 46. asynchronous non-multiplexed sram/psram/nor write timings (1) 1. based on characterization, not tested in production symbol parameter min max unit t w(ne) fmc_ne low time 3thclk-1 3thclk+2 ns t v(nwe_ne) fmc_nex low to fmc_nwe low thclk+0.5 thclk+1 t w(nwe) fmc_nwe low time thclk-2 thclk+1 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time thclk-0.5 - t v(a_ne) fmc_nex low to fmc_a valid - 0 t h(a_nwe) address hold time after fmc_nwe high thclk-1.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 1 t h(bl_nwe) fmc_bl hold time after fmc_nwe high thclk-0.5 - t v(data_ne) data to fmc_nex low to data valid - thclk+ 3 t h(data_nwe) data hold time after fmc_nwe high thclk+0.5 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 2.5 t w(nadv) fmc_nadv low time - thclk+2 . " , $ a t a & - # ? . % x & - # ? . " , ; = & - # ? $ ; = t v " , ? . % t h $ a t a ? . 7 % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % t w . 7 % & - # ? . 7 % t v . 7 % ? . % t h . % ? . 7 % t h ! ? . 7 % t h " , ? . 7 % t v $ a t a ? . % t w . % - 3 6 & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 electrical characteristics stm32f303xd stm32f303xe 102/184 docid026415 rev 4 table 47. asynchronous non-multiplexed sram/psram/nor write-nwait timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(ne) fmc_ne low time 8thclk+1 8thclk+2 ns t w(nwe) fmc_nwe low time 6thclk-1 6thclk+2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5thclk-0.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4thclk+2 - table 48. asynchronous multiplexed psram/nor read-nwait timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(ne) fmc_ne low time 8thclk+2 8thclk+2 ns t w(noe) fmc_nwe low time 6thclk-1 6thclk+1.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 4thclk+6 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4thclk-4 - docid026415 rev 4 103/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 22. asynchronous multiplexed psram/nor read timings . " , $ a t a & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . % ! d d r e s s & - # ? ! ; = t v ! ? . % & - # ? . 7 % t v ! ? . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t s u $ a t a ? . % t h ! $ ? . ! $ 6 & - # ? . % & - # ? . / % t w . % t w . / % t v . / % ? . % t h . % ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % t h $ a t a ? . / % & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 electrical characteristics stm32f303xd stm32f303xe 104/184 docid026415 rev 4 table 49. asynchronous multiplexed psram/nor read timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(ne) fmc_ne low time 3thclk-0.5 3thclk+1 ns t v(noe_ne) fmc_nex low to fmc_noe low 2thclk 2thclk+1 t w(noe) fmc_noe low time thclk-2 thclk+2 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 1.5 t v(nadv_ne ) fmc_nex low to fmc_nadv low 0 2 t w(nadv) fmc_nadv low time thclk-2 thclk+2 t h(ad_nadv) fmc_ad(address) valid hold time after fmc_nadv high 0 - t h(a_noe) address hold time after fmc_noe high thclk-0.5 - t h(bl_noe) fmc_bl time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t su(data_ne) data to fmc_nex high setup time thclk - t su(data_noe) data to fmc_noe high setup time thclk+1 - t h(data_ne) data hold time after fmc_nex high 0 - t h(data_noe) data hold time after fmc_noe high 0 - docid026415 rev 4 105/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 23. asynchronous multip lexed psram/nor write timings . " , $ a t a & - # ? . % x & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . 7 % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % t w . 7 % & - # ? . 7 % t v . 7 % ? . % t h . % ? . 7 % t h ! ? . 7 % t h " , ? . 7 % t v ! ? . % t w . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t v $ a t a ? . ! $ 6 t h ! $ ? . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 electrical characteristics stm32f303xd stm32f303xe 106/184 docid026415 rev 4 synchronous waveforms and timings figure 24 and figure 27 present the synchro nous waveforms and table 52 to table 55 provide the corresponding timings. the result s shown in these tables are obtained with the following fsmc configuration: ? burstaccessmode = fmc_ burstaccessmode_enable; ? memorytype = fmc_memorytype_cram; ? writeburst = fmc_writeburst_enable; ? clkdivision = 1; ? datalatency = 2 for nor flash; datalatency = 0 for psram in all timing tables, the thclk is the hclk clock period (with maximum fmc_clk = 36 mhz). table 50. asynchronous multiplexed psram/nor write timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(ne) fmc_ne low time 4thclk-1 4thclk+1 ns t v(nwe_ne) fmc_nex low to fmc_nwe low thclk thclk+0.5 t w(nwe) fmc_nwe low time 2thclk-0.5 2thclk+1 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time thclk-0.5 - t v(a_ne) fmc_nex low to fmc_a valid - 5 t v(nadv_ne) fmc_nex low to fmc_nadv low 1 2.5 t w(nadv) fmc_nadv low time thclk-2 thclk+2 t h(ad_nadv) fmc_ad(adress) valid hold time after fmc_nadv high) thclk-2 - t h(a_nwe) address hold time after fmc_nwe high thclk-1 - t h(bl_nwe) fmc_bl hold time after fmc_nwe high thclk-0.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 1 t v(data_nadv) fmc_nadv high to data valid - thclk +3.5 t h(data_nwe) data hold time after fmc_nwe high thclk +0.5 - table 51. asynchronous multiplexed psram/nor write-nwait timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(ne) fmc_ne low time 9thclk 9thclk+0.5 ns t w(nwe) fmc_nwe low time 6thclk 6thclk+2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5thclk+6 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 5thclk-5 - docid026415 rev 4 107/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 24. synchronous multiplexed nor/psram read timings & - # ? # , + & - # ? . % x & - # ? . ! $ 6 & - # ? ! ; = & - # ? . / % & - # ? ! $ ; = ! $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + ( . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + ( ! ) 6 t d # , + , . / % , t d # , + ( . / % ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 electrical characteristics stm32f303xd stm32f303xe 108/184 docid026415 rev 4 table 52. synchronous multiple xed nor/psram read timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(clk) fmc_clk period 2thclk - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 5 t d(clkh_nexh) fmc_clk high to fmc_nex high (x= 0?2) thclk+1 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 7 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 2.5 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) -3 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-noel) fmc_clk low to fmc_noe low - 6 t d(clkh-noeh) fmc_clk high to fmc_noe high thclk+1 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 2 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t su(adv-clkh) fmc_a/d[15:0] valid data before fmc_clk high 4 - t h(clkh-adv) fmc_a/d[15:0] valid data after fmc_clk high 6 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 3 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 4 - docid026415 rev 4 109/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 25. synchronous multiplexed psram write timings & - # ? # , + & - # ? . % x & - # ? . ! $ 6 & - # ? ! ; = & - # ? . 7 % & - # ? ! $ ; = ! $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + ( . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + ( ! ) 6 t d # , + ( . 7 % ( t d # , + , . 7 % , t d # , + ( . " , ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 t d # , + , $ a t a & - # ? . " , electrical characteristics stm32f303xd stm32f303xe 110/184 docid026415 rev 4 table 53. synchronous multiplexed psram write timings (1) (2) 1. based on characterization, not tested in production. 2. c l = 30 pf. symbol parameter min max unit t w(clk) fmc_clk period, vdd range= 2.7 to 3.6 v 2thclk-1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 5.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) thclk+1 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 7 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 2 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) -0 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 5.5 t d(clkh-nweh) fmc_clk high to fmc_nwe high thclk+1 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 7.5 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t d(clkl-data) fmc_a/d[15:0] valid data after fmc_clk low -8 t d(clkl-nbll) fmc_clk low to fmc_nbl low - 6 t d(clkh-nblh) fmc_clk high to fmc_nbl high thclk+1 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 3 - t h(clkh-nwait ) fmc_nwait valid after fmc_clk high 5 - docid026415 rev 4 111/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 26. synchronous non-multiplexed nor/psram read timings & - # ? # , + & - # ? . % x & - # ? ! ; = & - # ? . / % & - # ? $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y t d # , + , . % x , t d # , + ( . % x ( t d # , + , ! 6 t d # , + ( ! ) 6 t d # , + , . / % , t d # , + ( . / % ( t s u $ 6 # , + ( t h # , + ( $ 6 t s u $ 6 # , + ( t h # , + ( $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 & - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( electrical characteristics stm32f303xd stm32f303xe 112/184 docid026415 rev 4 table 54. synchronous non-multiplexed nor/psram read timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(clk) fmc_clk period 2thclk-1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) thclk+1 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 7 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 2.5 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 7 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) thclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 6 t d(clkh-noeh) fmc_clk high to fmc_noe high thclk+1 - t su(dv-clkh) fmc_d[15:0] valid data before fmc_clk high 3.5 - t h(clkh-dv) fmc_d[15:0] valid data after fmc_clk high 5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 t h(clkh-nwait) fmc_nwait valid after fmc_clk high 4 docid026415 rev 4 113/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 27. synchronous non-multi plexed psram write timings - 3 6 & - # ? # , + & - # ? . % x & - # ? ! ; = & - # ? . 7 % & - # ? $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y t d # , + , . % x , t d # , + ( . % x ( t d # , + , ! 6 t d # , + ( ! ) 6 t d # , + ( . 7 % ( t d # , + , . 7 % , t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 & - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( t d # , + , $ a t a & - # ? . " , t d # , + ( . " , ( electrical characteristics stm32f303xd stm32f303xe 114/184 docid026415 rev 4 pc card/compactflash controller waveforms and timings figure 28 to figure 33 present the pc card/compact flash controller waveforms, and table 56 to table 57 provide the corresponding timings. the results shown in this table are obtained with the followin g fsmc configuration: ? com.fmc_setuptime = 0x04; ? com.fmc_waitsetuptime = 0x07; ? com.fmc_holdsetuptime = 0x04; ? com.fmc_hizsetuptime = 0x05; ? att.fmc_setuptime = 0x04; ? att.fmc_waitsetuptime = 0x07; ? att.fmc_holdsetuptime = 0x04; ? att.fmc_hizsetuptime = 0x05; ? io.fmc_setuptime = 0x04; ? io.fmc_waitsetuptime = 0x07; ? io.fmc_holdsetuptime = 0x04; ? io.fmc_hizsetuptime = 0x05; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the thclk is the hclk clock period. table 55. synchronous non-multiplexed psram write timings (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(clk) fmc_clk period 2thclk-1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 6 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) thclk+1.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 7.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 6.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 0 t d(clkh-nweh) fmc_clk high to fmc_nwe high thclk+2 - t d(clkl-data) fmc_d[15:0] valid data after fmc_clk low - 7.5 t d(clkl-nbll) fmc_clk low to fmc_nbl low - 7 t d(clkh-nblh) fmc_clk high to fmc_nbl high thclk+0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 4 - docid026415 rev 4 115/184 stm32f303xd stm32f303xe electrical characteristics 161 table 56. switching characteristics for pc card/cf read and write cycles in attribute/common space (1) 1. based on characterization, not tested in production. symbol parameter min max unit t v(ncex-a) fmc_ncex low to fmc_ay valid - 0 ns t h(ncex_ai) fmc_ncex high to fmc_ax invalid 2.5 - t d(nreg-ncex) fmc_ncex low to fmc_nreg valid - 2 t h(ncex-nreg) fmc_ncex high to fmc_nreg invalid 0 - t d(ncex-nwe) fmc_ncex low to fmc_nwe low - 5thclk+2 t w(nwe) fmc_nwe low width 8thclk 8thclk+0.5 t d(nwe_ncex) fmc_nwe high to fmc_ncex high 5thclk-1 - t v (nwe-d) fmc_nwe low to fmc_d[15:0] valid - 5 t h (nwe-d) fmc_nwe high to fmc_d[15:0] invalid 4thclk-1 - t d (d-nwe) fmc_d[15:0] valid before fmc_nwe high 13thclk-3 - t d(ncex-noe) fmc_ncex low to fmc_noe low 5thclk+2 t w(noe) fmc_noe low width 8thclk-1 8thclk+2 t d(noe_ncex) fmc_noe high to fmc_ncex high 5thclk-1 - t su (d-noe) fmc_d[15:0] valid data before fmc_noe high thclk+2 - t h(noe-d) fmc_n0e high to fmc_d[15:0] invalid 0 - electrical characteristics stm32f303xd stm32f303xe 116/184 docid026415 rev 4 figure 28. pc card/compactflash cont roller waveforms for common memory read access 1. fmc_nce4_2 remains high (inac tive during 8-bit access. figure 29. pc card/compactflash cont roller waveforms for common memory write access & - # ? . 7 % t w . / % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . # % ? . / % t s u $ . / % t h . / % $ t v . # % x ! t d . 2 % ' . # % x t d . ) / 2 $ . # % x t h . # % x ! ) t h . # % x . 2 % ' t h . # % x . ) / 2 $ t h . # % x . ) / 7 2 - 3 6 - 3 6 t d . # % ? . 7 % t w . 7 % t h . 7 % $ t v . # % ? ! t d . 2 % ' . # % ? t d . ) / 2 $ . # % ? t h . # % ? ! ) - % - x ( ) : t v . 7 % $ t h . # % ? . 2 % ' t h . # % ? . ) / 2 $ t h . # % ? . ) / 7 2 & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . 7 % . # % ? t d $ . 7 % & - # ? . # % ? ( i g h docid026415 rev 4 117/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 30. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). - 3 6 t d . # % ? . / % t w . / % t s u $ . / % t h . / % $ t v . # % ? ! t h . # % ? ! ) t d . 2 % ' . # % ? t h . # % ? . 2 % ' & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . / % . # % ? ( i g h electrical characteristics stm32f303xd stm32f303xe 118/184 docid026415 rev 4 figure 31. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hi-z). table 57. switching characteristics for pc card/cf read and write cycles in i/o space (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(niowr) fmc_niowr low width 8thclk-0.5 ns t v(niowr-d) fmc_niowr low to fmc_d[15:0] valid - 5.5 t h(niowr-d) fmc_niowr high to fmc_d[15:0] invalid 4thclk-0.5 - t d(nce4_1-niowr) fmc_nce4_1 low to fmc_niowr valid - 5thclk+1 t h(ncex-niowr) fmc_ncex high to fmc_niowr invalid 4thclk+0.5 - t d(niord-ncex) fmc_ncex low to fmc_niord valid - 5thclk t h(ncex-niord) fmc_ncex high to fmc_niord) valid 6thclk+2 - t w(niord) fmc_niord low width 8thclk-1 8thclk+1 t su(d-niord) fmc_d[15:0] valid before fmc_niord high thclk+2 - t d(niord-d) fmc_d[15:0] valid after fmc_niord high 0- - 3 6 t w . 7 % t v . # % ? ! t d . 2 % ' . # % ? t h . # % ? ! ) t h . # % ? . 2 % ' t v . 7 % $ & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . 7 % . # % ? ( i g h t d . # % ? . 7 % docid026415 rev 4 119/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 32. pc card/compactflash controll er waveforms for i/o space read access figure 33. pc card/compactflash controller waveforms for i/o space write access - 3 6 t d . ) / 2 $ . # % ? t w . ) / 2 $ t s u $ . ) / 2 $ t d . ) / 2 $ $ t v . # % x ! t h . # % ? ! ) & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . # % ? . ) / 7 2 t w . ) / 7 2 t v . # % x ! t h . # % ? ! ) t h . ) / 7 2 $ ! 4 4 x ( ) : t v . ) / 7 2 $ - 3 6 & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ electrical characteristics stm32f303xd stm32f303xe 120/184 docid026415 rev 4 nand controller waveforms and timings figure 34 and figure 35 present the nand controller synchronous waveforms, and table 58 and table 59 provide the corresponding timings. the results shown in this table are obtained with the follo wing fsmc configuration: ? com.fmc_setuptime = 0x01; ? com.fmc_waitsetuptime = 0x03; ? com.fmc_holdsetuptime = 0x02; ? com.fmc_hizsetuptime = 0x03; ? att.fmc_setuptime = 0x01; ? att.fmc_waitsetuptime = 0x03; ? att.fmc_holdsetuptime = 0x02; ? att.fmc_hizsetuptime = 0x03; ? bank = fmc_bank_nand; ? memorydatawidth = fmc_memorydatawidth_16b; ? ecc = fmc_ecc_enable; ? eccpagesize = fmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the thclk is the hclk clock period. figure 34. nand controller read timings & - # ? . 7 % & - # ? . / % . 2 % & - # ? $ ; = t s u $ . / % t h . / % $ - 3 6 ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . / % t h . / % ! , % docid026415 rev 4 121/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 35. nand controller write timings table 58. switching characteristics for nand flash read cycles (1) (2) 1. based on characterization, not tested in production. 2. cl = 30 pf symbol parameter min max unit t w(noe) fmc_noe low width 6thclk 6thclk + 2 ns t su(d-noe) fmc_d[15-0] valid data before fmc_noe high thclk+5 - t h(noe-d) fmc_d[15-0] valid data after fmc_noe high 0- t d(ale-noe) fmc_ale valid before fmc_noe low - 6thclk -0.5 t h(noe-ale) fmc_nwe high to fmc_ale invalid 6thclk-1 - table 59. switching characteristics for nand flash write cycles (1) 1. based on characterization, not tested in production. symbol parameter min max unit t w(nwe) fmc_nwe low width 4thclk-0.5 4thclk + 1.5 ns t v(nwe-d) fmc_nwe low to fmc_d[15-0] valid - 3.5 t h(nwe-d) fmc_nwe high to fmc_d[15-0] invalid 3thclk -1.5 - t d(d-nwe) fmc_d[15-0] valid before fmc_nwe high 5thclk ? 3 - t d(ale_nwe) fmc_ale valid before fmc_nwe low - 4thclk+2 t h(nwe-ale) fmc_nwe high to fmc_ale invalid 2thclk-1 - - 3 6 t h . 7 % $ t v . 7 % $ & - # ? . 7 % & - # ? . / % . 2 % & - # ? $ ; = ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . 7 % t h . 7 % ! , % electrical characteristics stm32f303xd stm32f303xe 122/184 docid026415 rev 4 6.3.12 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling two leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 60 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and pre qualification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) table 60. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-4 4a docid026415 rev 4 123/184 stm32f303xd stm32f303xe electrical characteristics 161 pre qualification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.13 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. table 61. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/72 mhz s emi peak level v dd = 3.6 v, t a = 25 c, lqfp144 package compliant with iec 61967-2 0.1 to 30 mhz 7 dbv 30 to 130 mhz 15 130 mhz to 1ghz 31 sae emi level 4 - table 62. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to ansi/jedec js-001 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 c3 250 electrical characteristics stm32f303xd stm32f303xe 124/184 docid026415 rev 4 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.14 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failu re (for example reset occurrence or oscillator frequency deviation). the test results are given in table 64 . table 63. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a docid026415 rev 4 125/184 stm32f303xd stm32f303xe electrical characteristics 161 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 64. i/o current in jection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 -0 na ma injected current on pf3, pc1, pc2, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pb0 , pb1, pe8, pe9, pe10, pe11, pe12, pe13, pe14, pe15, pb13, pb14, pb15, pd8, pd9, pd10, pd11, pd12, pd13, pd14 pins with induced leakage current on adjacent pins less than - 50 a or more than +400 a -5 +5 injected current on pf2, pf4, pc0, pc1, pc2, pc3, pa0, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pc4, pc5, pb2, pb11 with induced leakage current on other pins from this group less than -50 a or more than +400 a -5 +5 injected current on pb0, pb1, pe7, pe8, pe9, pe10, pe11, pe12, pe13, pe14, pe15, pb12, pb13, pb14, p15, pd8, pd9, pd10, pd 11, pd12, pd13, pd14 with induced leakage current on other pins from this group less than -50 a or more than +400 a -5 +5 injected current on any other ft and ftf pins -5 na injected current on any other pins -5 +5 electrical characteristics stm32f303xd stm32f303xe 126/184 docid026415 rev 4 6.3.15 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 65 are derived from tests performed under the conditions summarized in table 19 . all i/os are cmos and ttl compliant. table 65. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v dd +0.07 (1) v ft and ftf i/o - - 0.475 v dd -0.2 (1) boot0 - - 0.3 v dd ?0.3 (1) all i/os except boot0 - - 0.3 v dd (2) v ih high level input voltage tc and tta i/o 0.445 v dd +0.398 (1) -- v ft and ftf i/o 0.5 v dd +0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 0.7 v dd (2) -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (3) tc, ft and ftf i/o tta i/o in digital mode v ss v in v dd --0.1 a tta i/o in digital mode v dd v in v dda --1 tta i/o in analog mode v ss v in v dda --0.2 ft and ftf i/o (4) v dd v in 5 v --10 r pu weak pull-up equivalent resistor (5) v in = v ss 25 40 55 k r pd weak pull-down equivalent resistor (5) v in = v dd 25 40 55 k c io i/o pin capacitance - - 5 - pf 1. data based on design simulation. 2. tested in production. 3. leakage could be higher than the maximum value. if n egative current is injected on adjacent pins. refer to table 64: i/o current injection susceptibility . 4. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. 5. pull-up and pull-down resistors are designed with a true re sistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order). docid026415 rev 4 127/184 stm32f303xd stm32f303xe electrical characteristics 161 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 36 and figure 37 for standard i/os. figure 36. tc and tta i/o input characteristics - cmos port figure 37. tc and tta i/o input characteristics - ttl port figure 38. five volt tole rant (ft and ftf) i/o input characteristics - cmos port 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 h v w h g l q s u r g x f w l r q 7 h v w h g l q s u r g x f w l r q % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 9 , / p d [ 9 ' ' 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v 0 6 9 9 ' ' 9 9 , / 9 , + 9 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v 7 h v w h g l q s u r g x f w l r q & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q electrical characteristics stm32f303xd stm32f303xe 128/184 docid026415 rev 4 figure 39. five volt tolerant (ft and ftf) i/o input characteristics - ttl port 0 6 9 9 ' ' 9 9 , / 9 , + 9 9 , / p l q 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v docid026415 rev 4 129/184 stm32f303xd stm32f303xe electrical characteristics 161 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 17 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 17 ). output voltage levels unless otherwise specified, the parameters given in table 66 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . all i/os (ft, tta and tc unless otherwise specified) are cmos and ttl compliant. table 66. output voltage characteristics symbol parameter conditions min max unit v ol (1) output low level voltage for an i/o pin cmos port (2) i io = +48 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin v dd ?1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +6 ma 2 v < v dd < 2.7 v -0.4 v oh (3)(4) output high level voltage for an i/o pin v dd ?0.4 - v olfm+ (4)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = +20 ma 2.7 v < v dd < 3.6 v -0.4 1. the i io current sunk by the device must always res pect the absolute maximum rating specified in table 17 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. the i io current sourced by the device must always re spect the absolute maximu m rating specified in table 17 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 4. data based on design simulation. electrical characteristics stm32f303xd stm32f303xe 130/184 docid026415 rev 4 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 40 and table 67 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 19 . table 67. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v - 125 (3) ns t r(io)out output low to high level rise time - 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 10 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -25 (3) ns t r(io)out output low to high level rise time -25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v - 50 (3) mhz c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 20 (3) t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 to 3.6 v -2 (4) mhz t f(io)out output high to low level fall time -12 (4) ns t r(io)out output low to high level rise time -34 (4) -t extipw pulse width of external signals detected by the exti controller -10 (3) -ns 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the rm0316 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 40 . 3. guaranteed by design, not tested in production. 4. the i/o speed configuration is bypassed in fm+ i/o mode. refer to the reference manual rm0316 for a description of fm+ i/o mode configuration. docid026415 rev 4 131/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 40. i/o ac charac teristics definition 1. see table 67: i/o ac characteristics . 6.3.16 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 65 ). unless otherwise specified, the parameters given in table 68 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . w u , 2 r x w 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / 7 w i , 2 r x w . 4 7 table 68. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage - - - 0.3v dd + 0.07 (1) v v ih(nrst) (1) nrst input high level voltage - 0.445v dd + 0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis - - 200 - mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k v f(nrst) (1) nrst input filtered pulse - - - 100 (1) ns v nf(nrst) (1) nrst input not filtered pulse - 500 (1) --ns 1. guaranteed by design, not tested in production. 2. the pull-up is designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . electrical characteristics stm32f303xd stm32f303xe 132/184 docid026415 rev 4 figure 41. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 68 . otherwise the reset will not be taken into account by the device. 6.3.17 timer characteristics the parameters given in table 69 are guaranteed by design. refer to section 6.3.15: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 0 6 9 ( [ w h u q d o u h v h w f l u f x l w u \ 1 5 6 7 ? ) 9 ' ' 5 3 8 ) l o w h u , q w h u q d o u h v h w table 69. timx (1)(2) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim4, tim8, tim15, tim16, tim17 and tim20 timers. 2. guaranteed by design, not tested in production. symbol parameter conditions min max unit t res(tim) timer resolution time -1- t timxclk f timxclk = 72 mhz 13.9 - ns f timxclk = 144 mhz 6.95 - ns f ext timer external clock frequency on ch1 to ch4 -0 f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim timer resolution timx (except tim2) - 16 bit tim2 - 32 t counter 16-bit counter clock period - 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s f timxclk = 144 mhz 0.0069 455 s t max_count maximum possible count with 32-bit counter - - 65536 65536 t timxclk f timxclk = 72 mhz - 59.65 s f timxclk = 144 mhz - 29.825 s docid026415 rev 4 133/184 stm32f303xd stm32f303xe electrical characteristics 161 table 70. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller inter nal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so t hat there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout (ms) rl[11:0]= 0x000 max timeout (ms) rl[11:0]= 0xfff /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 table 71. wwdg min-max timeout value @72 mhz (pclk) (1) 1. guaranteed by design, not tested in production. prescaler wdgtb min timeout value max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 electrical characteristics stm32f303xd stm32f303xe 134/184 docid026415 rev 4 6.3.18 communications interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev.03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1mbits/s the i 2 c timings requirements are guaranteed by design when the i 2 c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are ?true? open-drain. when conf igured as open-drain, the pmos connected between the i/o pin and vddiox is disabled, but is still pr esent. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.15: i/o port characteristics . all i 2 c i/os embed an analog filter. refer to the table 72: i2c analog filter characteristics . table 72. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af pulse width of spikes that are suppressed by the analog filter 50 260 ns docid026415 rev 4 135/184 stm32f303xd stm32f303xe electrical characteristics 161 spi/i 2 s characteristics unless otherwise specified, the parameters given in table 73 for spi or in table 74 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 19 . refer to section 6.3.15: i/o port characteristics for more details on the input/output alternate function characteristics (n ss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 73. spi characteristics (1) symbol parameter conditions min typ. max unit f sck 1/t c(sck) spi clock frequency master mode 2.7 v docid026415 rev 4 137/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 44. spi timing diagram - master mode (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 table 74. i 2 s characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256 x 8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % electrical characteristics stm32f303xd stm32f303xe 138/184 docid026415 rev 4 note: refer to the i2s section in rm0316 refere nce manual for more details about the sampling frequency (fs), f mck , f ck , dck values reflect only the digital peripheral behavior, source clock precision might slightly change the va lues dck depends main ly on odd bit value. digital contribution leads to a min of (i2sdiv/(2*i2sdi v+odd) and a max (i2sdiv+odd)/(2*i2sdiv+odd) and fs max supported for each mode/condition. t v(ws) ws valid time master mode - 20 ns t h(ws) ws hold time master mode 2 - t su(ws) ws setup time slave mode 0 - t h(ws) ws hold time slave mode 4 - t su(sd_mr) data input setup time master receiver 1 - t su(sd_sr) slave receiver 1 - t h(sd_mr) data input hold time master receiver 8 - t h(sd_sr) slave receiver 2.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) -50 t v(sd_mt) master transmitter (after enable edge) -22 t h(sd_st) data output hold time slave transmitter (after enable edge) 8- t h(sd_mt) master transmitter (after enable edge) 1- 1. data based on characterization results, not tested in production. 2. 256xfs maximum is 36 mhz (apb1 maximum frequency) table 74. i 2 s characteristics (1) (continued) symbol parameter conditions min max unit docid026415 rev 4 139/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 45. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 46. i 2 s master timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t electrical characteristics stm32f303xd stm32f303xe 140/184 docid026415 rev 4 usb characteristics figure 47. usb timings: definition of data signal rise and fall time table 75. usb startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb transceiver startup time 1 s table 76. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 full-speed electrical specification, the usb_dp (d+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 v voltage range. -3.0 (3) 3. the stm32f303xd/e usb functionality is ensured dow n to 2.7 v but not the full usb electrical characteristics which are degr aded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by design, not tested in production. differential input sensitivity i(usb_dp, usb_dm) 0.2 - v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold - 1.3 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (5) 5. r l is the load connected on the usb drivers. -0.3 v v oh static output level high r l of 15 k to v ss (5) 2.8 3.6 d l e & u r v v r y h u s r l q w v ' l i i h u h q w l d o g d w d o l q h v 9 & 5 6 9 6 6 w i w u table 77. usb: full-speed electrical characteristics (1) symbol parameter conditions min typ max unit driver characteristics t r rise time (2) c l = 50 pf 4 - 20 ns t f fall time (2) c l = 50 pf 4 - 20 ns docid026415 rev 4 141/184 stm32f303xd stm32f303xe electrical characteristics 161 can (controller area network) interface refer to section 6.3.15: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). 6.3.19 adc characteristics unless otherwise specified, the parameters given in table 78 to table 81 are guaranteed by design, with conditio ns summarized in table 19 . t rfm rise/ fall time matching t r /t f 90 - 110 % v crs output signal crossover voltage - 1.3 - 2.0 v output driver impedance (3) z drv driving high and low 28 40 44 1. guaranteed by design, not tested in production. 2. measured from 10% to 90% of the data signal. for more detaile d informations, please refer to usb specification - chapter 7 (version 2.0). 3. no external termination series resistors are required on usb_dp (d+) and usb_dm (d-), the matching impedance is already included in the embedded driver. table 77. usb: full-speed electrical characteristics (1) (continued) symbol parameter conditions min typ max unit table 78. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc -2.0-3.6v i dda current on vdda pin (see figure 48 ) single-ended mode, 5 msps - 907 1033 a single-ended mode, 1 msps - 194 285.5 single-ended mode, 200 ksps -51.570 differential mode, 5 msps - 887.5 1009 differential mode, 1 msps - 212 285 differential mode, 200 ksps -5169.5 electrical characteristics stm32f303xd stm32f303xe 142/184 docid026415 rev 4 i ref current on vref+ pin (see figure 49 ) single-ended mode, 5 msps - 104 139 a single-ended mode, 1 msps -20.437 single-ended mode, 200 ksps - 3.3 11.3 differential mode, 5 msps - 174 235 differential mode, 1 msps -34.652.6 differential mode, 200 ksps -613.6 v ref+ positive reference voltage - 2 - v dda v f adc adc clock frequency - 0.14 - 72 mhz f s (1) sampling rate resolution = 12 bits, fast channel 0.01 - 5.14 msps resolution = 10 bits, fast channel 0.012 - 6 resolution = 8 bits, fast channel 0.014 - 7.2 resolution = 6 bits, fast channel 0.0175 - 9 f trig (1) external trigger frequency f adc = 72 mhz resolution = 12 bits --5.14mhz resolution = 12 bits - - 14 1/f adc v ain conversion voltage range (2) -0-v ref+ v r ain (1) external input impedance - - - 100 k c adc (1) internal sample and hold capacitor --5-pf t stab (1) power-up time - 0 0 1 s t cal (1) calibration time f adc = 72 mhz 1.56 s - 112 1/f adc t latr (1) trigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2 1/f adc ckmode = 10 - - 2.25 1/f adc ckmode = 11 - - 2.125 1/f adc t latrinj (1) trigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3 1/f adc ckmode = 10 - - 3.25 1/f adc ckmode = 11 - - 3.125 1/f adc table 78. adc characteristics (continued) symbol parameter conditions min typ max unit docid026415 rev 4 143/184 stm32f303xd stm32f303xe electrical characteristics 161 figure 48. adc typical current consumption on vdda pin t s (1) sampling time f adc = 72 mhz 0.021 - 8.35 s - 1.5 - 601.5 1/f adc t adcvreg _stup (1) adc voltage regulator start-up time ---10s t conv (1) total conversion time (including sampling time) f adc = 72 mhz resolution = 12 bits 0.19 - 8.52 s resolution = 12 bits 14 to 614 (t s for sampling + 12.5 for successive approximation) 1/f adc 1. data guaranteed by design, not tested in production. 2. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pinouts and pin description for further details. table 78. adc characteristics (continued) symbol parameter conditions min typ max unit & o r f n i u h t x h q f \ 0 6 3 6 $ ' & f x u u h q w f r q v x p s w l r q ? $ 0 6 9 ' l i i h u h q w l d o p r g h 6 l q j o h h q g h g p r g h electrical characteristics stm32f303xd stm32f303xe 144/184 docid026415 rev 4 figure 49. adc typical curren t consumption on vref+ pin & o r f n i u h t x h q f \ 0 6 3 6 $ ' & f x u u h q w f r q v x p s w l r q ? $ 0 6 9 6 l q j o h h q g h g p r g h ' l i i h u h q w l d o p r g h table 79. maximum adc r ain (1) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ) fast channels (2) slow channels other channels (3) 12 bits 1.5 20.83 0.018 na na 2.5 34.72 0.150 na 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 10 bits 1.5 20.83 0.082 na na 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 docid026415 rev 4 145/184 stm32f303xd stm32f303xe electrical characteristics 161 8 bits 1.5 20.83 0.150 na 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 6 bits 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. data based on characterization results, not tested in production. 2. all fast channels, expect channels on pa2, pa6, pb1, pb12. 3. fast channels available on pa2, pa6, pb1, pb12. table 79. maximum adc r ain (1) (continued) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ) fast channels (2) slow channels other channels (3) electrical characteristics stm32f303xd stm32f303xe 146/184 docid026415 rev 4 table 80. adc accuracy - limited test conditions, 100-/144-pin packages (1)(2) symbol parameter conditions min (3) typ max (3) unit et to ta l unadjusted error adc clock freq. 72 mhz sampling freq. 5 msps v dda = v ref+ = 3.3 v 25c 100-pin/144-pin package single ended fast channel 5.1 ms - 3.5 4.5 lsb slow channel 4.8 ms - 4 4.5 differential fast channel 5.1 ms - 3 3 slow channel 4.8 ms - 3 3 eo offset error single ended fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 2.5 differential fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 1.5 eg gain error single ended fast channel 5.1 ms - 3 4 slow channel 4.8 ms - 3.5 4 differential fast channel 5.1 ms - 1.5 2.5 slow channel 4.8 ms - 2 2.5 ed differential linearity error single ended fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 1.5 differential fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 el integral linearity error single ended fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 1.5 3 differential fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 1.5 enob (4) effective number of bits single ended fast channel 5.1 ms 10.7 10.8 - bits slow channel 4.8 ms 10.7 10.8 - differential fast channel 5.1 ms 11.2 11.3 - slow channel 4.8 ms 11.1 11.3 - sinad (4) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - docid026415 rev 4 147/184 stm32f303xd stm32f303xe electrical characteristics 161 snr (4) signal-to- noise ratio adc clock freq. 72 mhz sampling freq 5 msps v dda = v ref+ = 3.3 v 25c 100-pin/144-pin package single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - thd (4) to ta l harmonic distortion single ended fast channel 5.1 ms - -76 -76 slow channel 4.8 ms - -76 -76 differential fast channel 5.1 ms - -80 -80 slow channel 4.8 ms - -80 -80 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative cu rrent on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.15 does not affect the adc accuracy. 3. data based on characterization re sults, not tested in production. 4. value measured with a -0.5 db full scale 50 khz sine wave input signal. table 80. adc accuracy - limited te st conditions, 100-/144-pin packages (1)(2) (continued) symbol parameter conditions min (3) typ max (3) unit electrical characteristics stm32f303xd stm32f303xe 148/184 docid026415 rev 4 table 81. adc accuracy, 100-pin/144-pin packages (1)(2)(3) symbol parameter conditions min (4) max (4) unit et to ta l unadjusted error adc clock freq. 72 mhz, sampling freq. 5 msps 2.0 v v dda , v ref+ 3.6 v 100-pin/144-pin package single ended fast channel 5.1 ms - 6.5 lsb slow channel 4.8 ms - 6.5 differential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4 eo offset error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2 eg gain error single ended fast channel 5.1 ms - 6 slow channel 4.8 ms - 6 differential fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 ed differential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 differential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 el integral linearity error single ended fast channel 5.1 ms - 2 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2 enob (5) effective number of bits single ended fast channel 5.1 ms 10.4 - bits slow channel 4.8 ms 10.2 - differential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - docid026415 rev 4 149/184 stm32f303xd stm32f303xe electrical characteristics 161 sinad (5) signal-to- noise and distortion ratio adc clock freq. 72 mhz, sampling freq. 5 msps, 2.0 v v dda , v ref+ 3.6 v 100-pin/144-pin package single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 63 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - snr (5) signal-to- noise ratio single ended fast channel 5.1 ms 64 - slow channel 4.8 ms 64 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd (5) to ta l harmonic distortion single ended fast channel 5.1 ms - 74 slow channel 4.8 ms - -74 differential fast channel 5.1 ms - -78 slow channel 4.8 ms - -76 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 6.3.15 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. 5. value measured with a -0.5 db full scale 50 khz sine wave input signal. table 81. adc accuracy, 10 0-pin/144-pin packages (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit electrical characteristics stm32f303xd stm32f303xe 150/184 docid026415 rev 4 table 82. adc accuracy - limited test conditions, 64-pin packages (1)(2) symbol parameter conditions min (3) typ max (3) unit et to ta l unadjusted error adc clock freq. 72 mhz sampling freq. 5 msps v dda = 3.3 v 25c 64-pin package single ended fast channel 5.1 ms - 4 4.5 lsb slow channel 4.8 ms - 5.5 6 differential fast channel 5.1 ms - 3.5 4 slow channel 4.8 ms - 3.5 4 eo offset error single ended fast channel 5.1 ms - 2 2 slow channel 4.8 ms - 1.5 2 differential fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 1.5 2 eg gain error single ended fast channel 5.1 ms - 3 4 slow channel 4.8 ms - 5 5.5 differential fast channel 5.1 ms - 3 3 slow channel 4.8 ms - 3 3.5 ed differential linearity error single ended fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 differential fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 el integral linearity error single ended fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 2 3 differential fast channel 5.1 ms - 1.5 1.5 slow channel 4.8 ms - 1.5 2 enob (4) effective number of bits single ended fast channel 5.1 ms 10.8 10.8 - bit slow channel 4.8 ms 10.8 10.8 - differential fast channel 5.1 ms 11.2 11.3 - slow channel 4.8 ms 11.2 11.3 - sinad (4) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - docid026415 rev 4 151/184 stm32f303xd stm32f303xe electrical characteristics 161 snr (4) signal-to- noise ratio adc clock freq. 72 mhz sampling freq 5 msps v dda = 3.3 v 25c 64-pin package single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - thd (4) to ta l harmonic distortion single ended fast channel 5.1 ms - -80 -80 slow channel 4.8 ms - -78 -77 differential fast channel 5.1 ms - -83 -82 slow channel 4.8 ms - -81 -80 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.15 does not affect the adc accuracy. 3. data based on characterization re sults, not tested in production. 4. value measured with a -0.5 db full scale 50 khz sine wave input signal. table 82. adc accuracy - limited test conditions, 64-pin packages (1)(2) (continued) symbol parameter conditions min (3) typ max (3) unit electrical characteristics stm32f303xd stm32f303xe 152/184 docid026415 rev 4 table 83. adc accuracy, 64-pin packages (1)(2)(3) symbol parameter conditions min (4) max (4) unit et to ta l unadjusted error adc clock freq. 72 mhz, sampling freq. 5 msps 2.0 v v dda 3.6 v 64-pin package single ended fast channel 5.1 ms - 6.5 lsb slow channel 4.8 ms - 6.5 differential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4.5 eo offset error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2.5 slow channel 4.8 ms - 2.5 eg gain error single ended fast channel 5.1 ms - 6 slow channel 4.8 ms - 6 differential fast channel 5.1 ms - 3.5 slow channel 4.8 ms - 4 ed differential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 differential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 el integral linearity error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3.5 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2.5 enob (5) effective number of bits single ended fast channel 5.1 ms 10.4 - bits slow channel 4.8 ms 10.4 - differential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - sinad (5) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 63 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - docid026415 rev 4 153/184 stm32f303xd stm32f303xe electrical characteristics 161 snr (5) signal-to- noise ratio adc clock freq. 72 mhz, sampling freq 5 msps, 2.0 v v dda 3.6 v 64-pin package single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 64 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd (5) to ta l harmonic distortion single ended fast channel 5.1 ms - -75 slow channel 4.8 ms - -75 differential fast channel 5.1 ms - -79 slow channel 4.8 ms - -78 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the ac curacy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.15 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. 5. value measured with a -0.5 db full scale 50 khz sine wave input signal. table 83. adc accuracy, 64-pin packages (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit table 84. adc accuracy at 1msps (1)(2) symbol parameter test conditions typ max (3) unit et total unadjusted error adc freq 72 mhz sampling freq 1msps 2.4 v v dda = v ref+ 3.6 v single-ended mode fast channel 2.5 5 lsb slow channel 3.5 5 eo offset error fast channel 1 2.5 slow channel 1.5 2.5 eg gain error fast channel 2 3 slow channel 3 4 ed differential linearity error fast channel 0.7 2 slow channel 0.7 2 el integral linearity error fast channel 1 3 slow channel 1.2 3 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any analog input pi ns should be avoided as this significantly reduces the ac curacy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentia lly inject negative current. any positive injection current within the limits specified for iinj(pin) and iinj(pin) in section 6.3.15: i/o port characteristics does not affect the adc accuracy. 3. data based on characterization results, not tested in production. electrical characteristics stm32f303xd stm32f303xe 154/184 docid026415 rev 4 figure 50. adc accuracy characteristics figure 51. typical connecti on diagram using the adc 1. refer to table 78 for the values of r ain . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 12 . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. a i c % / % ' , 3 " ) $ % ! , % 4 % $ % , 6 $ $ ! 6 3 3 ! 6 2 % & o r d e p e n d i n g o n p a c k a g e = 6 $ $ ! ; , 3 " ) $ % ! , e l w f r q y h u w h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u 5 $ , 1 $ , 1 [ 9 $ , 1 & s d u d v l w l f 9 ' ' 9 7 9 9 7 9 , / ? ? $ 5 $ ' & & $ ' & 0 6 9 docid026415 rev 4 155/184 stm32f303xd stm32f303xe electrical characteristics 161 6.3.20 dac electri cal specifications table 85. dac characteristics symbol parameter conditions min typ max unit v dda analog supply voltage dac output buffer on 2.4 - 3.6 v r load (1) resistive load dac output buffer on 5 - - k r o (1) output impedance dac output buffer on - - 15 k c load (1) capacitive load dac output buffer on - - 50 pf v dac_out (1) voltage on dac_out output corresponds to 12-bit input code (0x0e0) to (0xf1c) at v dda = 3.6 v and (0x155) and (0xeab) at v dda = 2.4 v dac output buffer on. 0.2 - v dda ? 0.2 v dac output buffer off - 0.5 v dda - 1lsb mv i ref dac dc current consumption in quiescent mode (standby mode) with no load, worst code (0xf1c) on the input - - 220 a i dda (3) dac dc current consumption in quiescent mode (standby mode) (2) with no load, middle code (0x800) on the input. - - 380 a with no load, worst code (0xf1c) on the input. - - 480 a dnl (3) differential non linearity difference between two consecutive code-1lsb) given for a 10-bit input code - - 0.5 lsb given for a 12-bit input code - - 2 lsb inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095) given for a 10-bit input code - - 1 lsb given for a 12-bit input code - - 4 lsb offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v dda /2) ---10mv given for a 10-bit input code at v dda = 3.6 v -- 3 lsb given for a 12-bit input code at v dda = 3.6 v -- 12lsb gain error (3) gain error given for a 12-bit input code - - 0.5 % t settling (3) settling time (full scale: for a 12-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb c load 50 pf, r load 5 k -3 4 s electrical characteristics stm32f303xd stm32f303xe 156/184 docid026415 rev 4 figure 52. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.21 comparator characteristics update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) c load 50 pf, r load 5 k -- 1 ms/s t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) c load 50 pf, r load 5 k -6.5 10 s psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement c load = 50 pf, no r load 5 k , - ?67 ?40 db 1. guaranteed by design, not tested in production. 2. quiescent mode refers to the state of the dac a keeping steady value on the output, so no dynamic consumption is involved. 3. data based on characterization results, not tested in production. table 85. dac characteristics (continued) symbol parameter conditions min typ max unit % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u % x i i h u h g q r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 5 / 2 $ ' & / 2 $ ' d l g table 86. comparator characteristics (1) symbol parameter conditions min. typ. max. unit v dda analog supply voltage - 2 - 3.6 v v in comparator input voltage range -0-v dda v bg scaler input voltage - - v refinit - v sc scaler offset voltage - - 5 10 mv t s_sc scaler startup time from power down ---0.2ms docid026415 rev 4 157/184 stm32f303xd stm32f303xe electrical characteristics 161 t start comparator startup time v dda 2.7 v - - 4 s v dda < 2.7 v - - 10 t d propagation delay for 200 mv step with 100 mv overdrive v dda 2.7 v - 25 28 ns v dda < 2.7 v - 28 30 propagation delay for full range step with 100 mv overdrive v dda 2.7 v - 32 35 v dda < 2.7 v - 35 40 v offset comparator offset error v dda 2.7 v - 5 10 mv v dda < 2.7 v - - 25 tv offset total offset variation full temperature range - - 3 mv i dda comp current consumption - - 400 600 a 1. guaranteed by design, not tested in production. table 86. comparator characteristics (1) (continued) symbol parameter conditions min. typ. max. unit electrical characteristics stm32f303xd stm32f303xe 158/184 docid026415 rev 4 6.3.22 operational am plifier char acteristics table 87. operational amplifier characteristics (1) symbol parameter condition min typ max unit v dda analog supply voltage - 2.4 - 3.6 v cmir common mode input range - 0 - v dda v vi offset input offset voltage maximum calibration range 25c, no load on output. --4 mv all voltage/temp. --6 after offset calibration 25c, no load on output. --1.6 all voltage/temp. --3 vi offset input offset voltage drift - - 5 - v/c i load drive current - - - 500 a i dda opamp consumption no load, quiescent mode - 690 1450 a ts_opamp_vout adc sampling time when reading the opamp output. - 400 - - ns cmrr common mode rejection ratio - - 90 - db psrr power supply rejection ratio dc 73 117 - db gbw bandwidth - - 8.2 - mhz sr slew rate - - 4.7 - v/s r load resistive load - 4 - - k c load capacitive load - - - 50 pf voh sat high saturation voltage r load = min, input at v dda . - - 100 mv r load = 20k, input at v dda . --20 vol sat low saturation voltage rload = min, input at 0v - - 100 rload = 20k, input at 0v. --20 ? m phase margin - - 62 - t offtrim offset trim time: during calibration, minimum time needed between two steps to have 1 mv accuracy ---2ms t wakeup wake up time from off state. c load 50 pf, r load 4 k , follower configuration -2.85s docid026415 rev 4 159/184 stm32f303xd stm32f303xe electrical characteristics 161 pga gain non inverting gain value - -2-- -4-- -8-- -16-- r network r2/r1 internal resistance values in pga mode (2) gain=2 - 5.4/5.4 - k gain=4 - 16.2/5.4 - gain=8 - 37.8/5.4 - gain=16 - 40.5/2.7 - pga gain error pga gain error - -1% - 1% i bias opamp input bias current - - - 0.2 (3) a pga bw pga bandwidth for different non inverting gain pga gain = 2, cload = 50pf, rload = 4 k -4- mhz pga gain = 4, cload = 50pf, rload = 4 k -2- pga gain = 8, cload = 50pf, rload = 4 k -1- pga gain = 16, cload = 50pf, rload = 4 k -0.5- en voltage noise density @ 1khz, output loaded with 4 k -109- @ 10khz, output loaded with 4 k -43- 1. guaranteed by design, not tested in production. 2. r2 is the internal resistance between opamp output and opamp inverting input. r1 is the internal resistance between opamp inverting input and ground. the pga gain =1+r2/r1 3. mostly tta i/o leakage, when used in analog mode. table 87. operational amplifier characteristics (1) (continued) symbol parameter condition min typ max unit nv hz ----------- electrical characteristics stm32f303xd stm32f303xe 160/184 docid026415 rev 4 figure 53. opamp voltage noise versus frequency docid026415 rev 4 161/184 stm32f303xd stm32f303xe electrical characteristics 161 6.3.23 temperature sensor characteristics 6.3.24 v bat monitoring characteristics table 88. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 2.2 - - s table 89. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 90. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q -1 - +1 % t s_vbat (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 2.2 - - s package information stm32f303xd stm32f303xe 162/184 docid026415 rev 4 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp144 package information figure 54. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # ! ? - % ? 6 ! ! ! , , c b ! docid026415 rev 4 163/184 stm32f303xd stm32f303xe package information 182 table 91. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.6890 - e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 package information stm32f303xd stm32f303xe 164/184 docid026415 rev 4 figure 55. lqfp144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. d l h docid026415 rev 4 165/184 stm32f303xd stm32f303xe package information 182 device marking for lqfp144 package the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 56. lqfp144 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. d ^???? s? 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l f d w l r q ' d w h f r g h < : : 6 7 0 ) = ( 7 5 5 h y l v l r q f r g h package information stm32f303xd stm32f303xe 166/184 docid026415 rev 4 7.2 ufbga100 package information figure 57. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not to scale. table 92. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.1 10 0.0020 0.0031 0.0043 a2 0.400 0.450 0.50 0 0.0157 0.0177 0.0197 a3 - 0.130 - - 0.0051 - a4 0.270 0.320 0.37 0 0.0106 0.0126 0.0146 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 d 6.950 7.000 7.050 0.2736 0.2756 0.2776 d1 5.450 5.500 5.55 0 0.2146 0.2165 0.2185 e 6.950 7.000 7.050 0.2736 0.2756 0.2776 e1 5.450 5.500 5.55 0 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - f 0.700 0.750 0.800 0.0276 0.0295 0.0315 $ & b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' 0 ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : $ e d o o l g h q w l i l h u h $ $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ $ $ e d o o l q g h [ d u h d docid026415 rev 4 167/184 stm32f303xd stm32f303xe package information 182 figure 58. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommend ed footprint note: non-solder mask defined (nsmd) pads are recommended. note: 4 to 6 mils solder paste screen printing process. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 93. ufbga100 recommended pcb design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 dpad 0.27 mm dsm 0.35 mm typ. (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter. table 92. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 0 6 9 ' v p ' s d g package information stm32f303xd stm32f303xe 168/184 docid026415 rev 4 device markin g for ufbga100 the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 59. ufbga100 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 3 u r g x f w l g h q w l i l f d w l r q % d o o l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 3 6 w d q g d u g 6 7 o r j r 4 5 . ' 7 & ) 0 6 9 docid026415 rev 4 169/184 stm32f303xd stm32f303xe package information 182 7.3 lqfp100 package information figure 60. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 1. drawing is not to scale. table 94. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0. 6220 0.6299 0.6378 d1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! package information stm32f303xd stm32f303xe 170/184 docid026415 rev 4 figure 61. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0. 6220 0.6299 0.6378 e1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 94. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c docid026415 rev 4 171/184 stm32f303xd stm32f303xe package information 182 device marking for lqfp100 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 62. lqfp100 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 3 u r g x f w l g h q w l i l f d w l r q 6 7 0 ) 9 ( 7 3 l q l g h q w l i l f d w l r q < : : ' d w h f r g h 5 5 h y l v l r q f r g h package information stm32f303xd stm32f303xe 172/184 docid026415 rev 4 7.4 wlcsp100 package information figure 63.wlcsp100 ? 100l, 4.775 x 5.041 mm 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. $ . : / & 6 3 b $ 5 b 0 ( b 9 $ 2 5 , ( 1 7 $ 7 , 2 1 5 ( ) ( 5 ( 1 & ( ) 5 2 1 7 9 , ( : % 2 7 7 2 0 9 , ( : 6 , ' ( 9 , ( : ' ( 7 $ , / $ $ % $ / / / 2 & $ 7 , 2 1 ; d d d 7 2 3 9 , ( : : $ ) ( 5 % $ & . 6 , ' ( 5 2 7 $ 7 ( ' ? ' ( 7 $ , / $ docid026415 rev 4 173/184 stm32f303xd stm32f303xe package information 182 table 95. wlcsp100 ? 100l, 4.775 x 5.041 mm 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max typ min max a 0.525 0.555 0.585 0. 0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.38 - - 0.0150 - a3 (2) 2. back side coating. - 0.025 - - 0.0010 - ? b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.22 0.25 0.28 - 0.0098 0.0110 d 4.74 4.775 4.81 - 0.1880 0.1894 e 5.006 5.041 5.076 - 0.1985 0.1998 e - 0.4 - - 0.0157 - e1 - 3.6 - - 0.1417 - e2 - 3.6 - - 0.1417 - f - 0.5875 - - 0.0231 - g - 0.7205 - - 0.0284 - n - 100 - - 3.9370 - aaa - 0.1 - - 0.0039 - bbb - 0.1 - - 0.0039 - ccc - 0.1 - - 0.0039 - ddd - 0.05 - - 0.0020 - eee - 0.05 - - 0.0020 - package information stm32f303xd stm32f303xe 174/184 docid026415 rev 4 figure 64. wlcsp100 ? 100l, 4.775 x 5.041 mm 0.4 mm pitch wafer level chip scale package recommended footprint table 96. wlcsp100 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 mm dpad 0.225 mm dsm 0.290 mm stencil thickness 0.1 mm : / & 6 3 b $ 5 b ) 3 b 9 ' s d g ' v p docid026415 rev 4 175/184 stm32f303xd stm32f303xe package information 182 device marking for wlcsp100 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 65. wlcsp100 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 ( 6 ) 9 ( < % d o o $ l g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q < : : 5 z ]?]}v } package information stm32f303xd stm32f303xe 176/184 docid026415 rev 4 7.5 lqfp64 package information figure 66. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 1. drawing is not to scale. table 97. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p docid026415 rev 4 177/184 stm32f303xd stm32f303xe package information 182 figure 67. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 97. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c package information stm32f303xd stm32f303xe 178/184 docid026415 rev 4 device marking for lqfp64 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 68. lqfp64 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h 6 7 0 ) 5 ( 7 z t t 5 docid026415 rev 4 179/184 stm32f303xd stm32f303xe package information 182 7.6 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 19: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum temperature in c, ? ja is the package junction-to- thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.6.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org 7.6.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed temperature at maximum dissipation and to a specific maximum junction temperature. as applications do not commonly use the stm32f 078x at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range is best suited to the application. table 98. package thermal characteristics symbol parameter value unit ja thermal resistance junction- lqfp144 - 20 20 mm 33 c/w thermal resistance junction- ufbga100 - 7 7 mm 59 thermal resistance junction- lqfp100 - 14 14 mm 42 thermal resistance junction- wlcsp100 - 0.4 mm pitch 44 thermal resistance junction- lqfp64 - 10 10 mm / 0.5 mm pitch 46 package information stm32f303xd stm32f303xe 180/184 docid026415 rev 4 the following examples show how to calculat e the temperature range needed for a given application. example 1: high-performance application assuming the following ap plication conditions: maximum temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in table 98 t jmax is calculated as follows: ? for lqfp100, 42 c/w t jmax = 82 c + (42 c/w 447 mw) = 82 c + 18.774 c = 100.774 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 6 (see section 8: part numbering ). note: with this given p dmax we can find the t amax allowed for a given device temperature range (order code suffix 6 or 7). suffix 6: t amax = t jmax - (42c/w 447 mw) = 105-18.774 = 86.226 c suffix 7: t amax = t jmax - (42c/w 447 mw) = 125-18.774 = 106.226 c example 2: high-temperature application using the same rules, it is poss ible to address applications that run at high temperature with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following ap plication conditions: maximum temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in table 98 t jmax is calculated as follows: ? for lqfp100, 42 c/w t jmax = 100 c + (42 c/w 134 mw) = 100 c + 5.628 c = 105.628 c this is above the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 7 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts. docid026415 rev 4 181/184 stm32f303xd stm32f303xe package information 182 refer to figure 69 to select the required temperature range (suffix 6 or 7) according to your temperature or power requirements. figure 69. lqfp100 p d max vs. t a 0 6 y 9 6 x i i l [ 6 x i i l [ 3 ' p : 7 $ ? & part numbering stm32f303xd stm32f303xe 182/184 docid026415 rev 4 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact the nearest st sales office. table 99. ordering information scheme example : stm32 f 303 v e t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 303 = stm32f303xx pin count r = 64 pins v = 100 pins z = 144 pins code size d = 384 kbytes of flash memory e = 512 kbytes of flash memory package h = ufbga t = lqfp y = wlcsp temperature range 6 = ?40 to 85 c 7 = ?40 to 105 c options xxx = programmed parts tr = tape and reel docid026415 rev 4 183/184 stm32f303xd stm32f303xe revision history 183 9 revision history table 100. document revision history date revision changes 20-jan-2015 1 initial release. 30-jan-2015 2 updated: ? table 13: stm32f303xd/e pin definitions ? table 14: stm32f303xd/e alternate function mapping ? table 37: hse oscillator characteristics ? figure 56: lqfp144 marking example (package top view) ? figure 62: lqfp100 marking example (package top view) 03-mar-2015 3 added usb_dm and usb_dp as additional function to pa11 and pa12 description, respectively in table 13: stm32f303xd/e pin definitions . updated: ? figure 56: lqfp144 marking example (package top view) , ? figure 59: ufbga100 marking example (package top view) , ? figure 62: lqfp100 marking example (package top view) . 08-dec-2015 4 renamed: ? fmc as fsmc, ? ccm ram as ccm sram. removed: ? table: i2c timings specification and figure: i2c bus ac waveforms and measurement circuit in section : i2c interface characteristics . ? added package information for wlcsp100 in section 7: package information . stm32f303xd stm32f303xe 184/184 docid026415 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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